Bank architecture for a non-volatile memory enabling simultaneous reading and writing

Claim 2

A flash memory device, comprising: at least two banks of flash memory cells; and means for simultaneously reading from one of said banks while writing to another of said banks; wherein: said means for simultaneously reading includes a state machine for performing an embedded method for erasing and programming, said means reads from one bank while said state machine erases another bank; said flash memory device includes an address input; and said means for simultaneously reading includes: control logic generating a control address, first decode logic receiving said address input and said control address, said first decode logic selectively using said address input or said control address to access a first bank of said at least two banks; and second decode logic receiving said address input and said control address, said second decode logic selectively using said address input or said control address to access said second bank of said at least two banks, said second decode logic being different from said first decode logic; said flash memory device further includes: a first sense amplifier circuit receiving read data from said first bank and read data from said second bank, said first sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate a read data output; and a second sense amplifier circuit receiving read data from said first bank and read data from said second bank, said second sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate verify data, said verify data being sent to said write control logic.

Claim 3

The flash memory device according to claim 1, further comprising: a multistate power supply that provides power based on an operation being performed on at least one of said at least two banks of flash memory cells.

Claim 4

The flash memory device according to claim 1, further comprising: an address buffer configured to store an address to be read from one of said at least two banks of flash memory cells; and an address sequencer configured to sequence a set of addresses to be at least one of programmed and verified in a second of said at least two banks of flash memory cells.

Claim 5

A non-volatile memory device capable of simultaneous reading and writing, comprising: a first set of memory cells; a second set of memory cells; and address logic having outputs including a first set of decoded lines and a second set of decoded lines, said address logic selectively using either a first address or a second address to access said first set of memory cells with said first set of decoded lines and selectively using either said first address or said second address to access said second set of memory cells with said second set of decoded lines; wherein: said first set of memory cells are flash memory cells; said second set of memory cells are flash memory cells; said flash memory device receives address and control information, said address input receiving said first address; said flash memory device further includes control logic receiving said control information, said control logic generating said second address and said control logic being in communication with said address logic; a first sense amplifier circuit receiving read data from said first set of flash memory cells and read data from said second set of flash memory cells, said first sense amplifier circuit selectively using said read data from said first set of flash memory cells and read data from said second set of flash memory cells to generate a read data output; and a second sense amplifier circuit receiving read data from said first set of flash memory cells and read data from said second set of flash memory cells, said second sense amplifier circuit selectively using said read data from said first set of flash memory cells and read data from said second set of flash memory cells to generate verify data, said verify data being sent to said control logic.

Claim 6

A non-volatile memory device capable of simultaneous reading and writing, comprising: a first set of memory cells; a second set of memory cells; and address logic having outputs including a first set of decoded lines and a second set of decoded lines, said address logic selectively using either a first address or a second address to access said first set of memory cells with said first set of decoded lines and selectively using either said first address or said second address to access said second set of memory cells with said second set of decoded lines; wherein: said first set of memory cells are flash memory cells; said second set of memory cells are flash memory cells; said flash memory device receives address and control information, said address input receiving said first address; said flash memory device further includes control logic receiving said control information, said control logic generating said second address and said control logic being in communication with said address logic; a first sense amplifier circuit receiving read data from said first set of flash memory cells and read data from said second set of flash memory cells, said first sense amplifier circuit selectively using said read data from said first set of flash memory cells and read data from said second set of flash memory cells to generate a read data output; and a second sense amplifier circuit receiving read data from said first set of flash memory cells and read data from said second set of flash memory cells, said second sense amplifier circuit selectively using said read data from said first set of flash memory cells and read data from said second set of flash memory cells to generate verify data, said verify data being sent to said control logic.

Claim 7

A non-volatile memory device according to claim 4, wherein: said first set of flash memory cells includes fourteen sectors of flash memory cells; and said second set of flash memory cells includes two sectors of flash memory cells.

Claim 8

A flash memory device according to claim 4, wherein: said second address being used as a program address.

Claim 9

A flash memory device according to claim 4, wherein: said second address being used as an erase address.

Claim 10

A flash memory device according to claim 4, wherein: said first set of flash memory cells being capable of performing a read while said second set of flash memory cells is performing a write; and said second set of flash memory cells being capable of performing a read while said first set of flash memory cells is performing a write.

Claim 11

A flash memory device according to claim 4, wherein: said flash memory device includes an address input and control logic, said address input receives said first address, said control logic generates said second address and said address logic includes: first decode logic receiving said first address and said second address, said first decode logic selectively using said address input or said write address to access said first set of flash memory cells with said first set of decoded lines; and second decode logic receiving said first address and said second address, said second decode logic selectively using said first address or said second address to access said second set of flash memory cells with said second set of decoded lines, said second decode logic being different from said first decode logic.

Claim 12

A flash memory according to claim 9, wherein: said first decode logic includes a multiplexer and a decoder, said multiplexer receives said first address and said second address, said decoder is in communication with said multiplexer and said first set of flash memory cells.

Claim 13

A flash member device according to claim 9, wherein: said control logic includes a state machine.

Claim 14

A flash memory device according to claim 4, wherein: said flash memory device includes an address input and a control input; said flash memory device further including control logic generating said second address, said control logic receiving said control input; and said address logic includes: a first multiplexer receiving said first address and said second address, said first multiplexer selecting either said first address or said second address based on a first signal from said control logic; a first word line decoder receiving a first subset of an output of said first multiplexer, a first bit line decoder receiving a second subset of said output of said first multiplexer, a second multiplexer receiving said first address and said second address, said second multiplexer selecting either said first address or said second address based on a second signal from said control logic; a second word line decoder receiving a first subset of an output of said second multiplexer, and a second bit line decoder receiving a second subset of said output of said second multiplexer.

Claim 15

A flash memory device according to claim 12, wherein: said address logic further includes a first sector decoder and a second sector decoder, said first sector decoder receiving a third subset of said output of said first multiplexer, said second sector decoder receiving a third subset of said output of said second multiplexer.

Claim 16

A flash memory device according to claim 12, further including: a third multiplexer capable of receiving read data from said first set of flash memory cells and read data from said second set of flash memory cells, said third multiplexer selecting either said read data from said first set of flash memory cells or said read data from said second set of flash memory cells based on a third control signal received from said control logic; a read sense amplifier receiving an output of said third multiplexer; a fourth multiplexer capable of receiving said read data from said first set of flash memory cells and said read data from said second set of flash memory cells, said fourth multiplexer selecting either said read data from said first set of flash memory cells or said read data from said second set of flash memory cells based on a fourth control signal received from said control logic; and a verify sense amplifier receiving an output of said fourth multiplexer.

Claim 17

A flash memory device according to claim 12, further including: a first sense amplifier circuit capable of receiving read data from said first set of flash memory cells and read data from said second set of flash memory cells, said first sense amplifier circuit selectively using said read data from said first set of flash memory cells and read data from said second set of flash memory cells to generate a read data output; and a second sense amplifier circuit capable of receiving said read data from said first set of flash memory cells and said read data from said second set of flash memory cells, said second sense amplifier circuit selectively using said read data from said first set of flash memory cells or read data from said second set of flash memory cells to generate verify data.

Claim 18

The non-volatile memory device according to claim 4, further comprising: a multistate power supply that provides power based on an operation being performed on at least one of said first and second sets of memory cells.

Claim 19

The non-volatile memory device according to claim 4, further comprising: an address buffer configured to store an address to be read from one of said first and second sets of flash memory cells; and an address sequencer configured to sequence a set of addresses to be at least one of programmed and verified in another of said first and second sets of flash memory cells.

Claim 20

A semiconductor non-volatile memory device, comprising: a first bank of sectors; a second bank of sectors, each sector of said first bank and said second bank including non-volatile memory cells; first address decode logic, said first address decode logic accessing said first bank; and second address decode logic, said second address decode logic accessing said second bank; wherein: said memory device receives an address input; said memory device further including a state machine for performing an embedded method for erasing and programming, said state machine generating a control address; said first bank being capable of using a first address from said address input to perform a read while said second bank is using said control address to perform a write; said second bank being capable of using said first address to perform a read while said first bank is using said control address to perform a write; and said semiconductor non-volatile memory device further comprising, a first sense amplifier circuit receiving read data from said first bank and read data from said second bank, said first sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate a read data output, and a second sense amplifier circuit receiving read data from said first bank and read data from said second bank, said second sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate verify data.

Claim 21

A semiconductor non-volatile memory device, comprising: a first bank of sectors; a second bank of sectors, each sector of said first bank and said second bank including non-volatile memory cells; first address decode logic, said first address decode logic accessing said first bank; and second address decode logic, said second address decode logic accessing said second bank; wherein: said memory device receives an address input; said memory device further including a state machine for performing an embedded method for erasing and programming, said state machine generating a control address; said first bank being capable of using a first address from said address input to perform a read while said second bank is using said control address to perform a write; said second bank being capable of using said first address to perform a read while said first bank is using said control address to perform a write; and said semiconductor non-volatile memory device further comprising, a first sense amplifier circuit receiving read data from said first bank and read data from said second bank, said first sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate a read data output, and a second sense amplifier circuit receiving read data from said first bank and read data from said second bank, said second sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate verify data.

Claim 22

The semiconductor non-volatile memory device according to claim 18, further comprising: a multistate power supply that provides power based on an operation being performed on at least one of said first and second banks of sectors.

Claim 23

The semiconductor non-volatile memory device according to claim 18, further comprising: an address buffer configured to store an address to be read from one of said first and second banks of sectors; and an address sequencer configured to sequence a set of addresses to be at least one of programmed and verified in another of said first and second banks of sectors.

Claim 26

The method according to claim 21, further comprising the step of: providing a multistate power supply that provides power based on an operation being performed on at least one of said banks.

Claim 27

The method according to claim 21, further comprising the steps of: loading addresses into a buffer, said addresses for reading from one of said banks of sectors; and sequencing an address sequencer through a set of addresses to be at least one of programmed or verified in another of said banks of sectors.

Claim 30

A method according to claim 24, wherein said step of writing includes an embedded erasing sequence.

Claim 31

The method according to claim 24, further comprising the step of: providing a multistate power supply that provides power based on an operation being performed on at least one of said first and second sets of flash memory cells.

Claim 34

The method according to claim 27, further comprising the step of: providing a multistate power supply that provides power based on an operation being performed on at least one of said first and second sets of memory cells.