US5952671A
Expired / Lapsed
US
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Small electrode for a chalcogenide switching device and method for fabricating same
Assignee: Round Rock Research LLC
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Filing: 1997-05-09
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Granted: 1999-09-14
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Expires: 2017-05-09
Abstract
Abstract A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.
Inventors
- 👤 Alan R. Reinberg
- 👤 Russell C. Zahorik, deceased
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:11
CPC Classifications
H; H10; H10B; H10B63/00; H10B63/20; H10B63/80; H10N; H10N70/00; H10N70/011; H10N70/061; H10N70/066; H10N70/068; H10N70/20; H10N70/231; H10N70/801; H10N70/821; H10N70/826; H10N70/881; H10N70/882; H10N70/8828
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
85 words
A memory cell comprising: an access device formed on a semiconductor substrate; a layer of dielectric material disposed on said access device, said layer of dielectric material having a pore therein, said pore being smaller than a photolithographic limit; a first layer of conductive material disposed within said pore to form a first electrode; a layer of structure changing material disposed on said first electrode; and a second layer of conductive material disposed on said layer of structure changing material to form a second electrode.
Claim 2
Dependent Claim
85 words
A memory cell comprising: an access device formed on a semiconductor substrate; a layer of dielectric material disposed on said access device, said layer of dielectric material having a pore therein, said pore being smaller than a photolithographic limit; a first layer of conductive material disposed within said pore to form a first electrode; a layer of structure changing material disposed on said first electrode; and a second layer of conductive material disposed on said layer of structure changing material to form a second electrode.
Claim 3
Dependent Claim
16 words
The memory cell, as set forth in claim 1, wherein said access device comprises a diode.
Claim 4
Dependent Claim
38 words
The memory cell, as set forth in claim 2, wherein said diode comprises: a layer of N doped polysilicon disposed on said substrate; and a layer of P+ doped polysilicon disposed on said layer of N doped polysilicon.
Claim 5
Dependent Claim
18 words
The memory cell, as set forth in claim 1, wherein said structure changing material comprises a chalcogenide material.
Claim 6
Dependent Claim
36 words
The memory cell, as set forth in claim 1, further comprising a layer of insulative material substantially surrounding said access device, said layer of dielectric material, said layer of structure changing material, and said second electrode.
Claim 7
Dependent Claim
21 words
The memory cell, as set forth in claim 1, wherein said layer of structure changing material is disposed in said pore.
Claim 8
Dependent Claim
133 words
A memory array comprising: a plurality of memory cells, each memory cell comprising: an access device formed on a semiconductor substrate; a layer of dielectric material disposed on said access device, said layer of dielectric material having a pore therein, said pore being smaller than a photolithographic limit; a first layer of conductive material disposed within said pore to form a first electrode; a layer of structure changing material disposed on said first electrode; and a second layer of conductive material disposed on said layer of structure changing material to form a second electrode; and a grid coupled to said plurality of memory cells, said grid formed by a first plurality of conductive lines generally extending in a first direction and a second plurality of conductive lines generally extending in a second direction.
Claim 9
Dependent Claim
133 words
A memory array comprising: a plurality of memory cells, each memory cell comprising: an access device formed on a semiconductor substrate; a layer of dielectric material disposed on said access device, said layer of dielectric material having a pore therein, said pore being smaller than a photolithographic limit; a first layer of conductive material disposed within said pore to form a first electrode; a layer of structure changing material disposed on said first electrode; and a second layer of conductive material disposed on said layer of structure changing material to form a second electrode; and a grid coupled to said plurality of memory cells, said grid formed by a first plurality of conductive lines generally extending in a first direction and a second plurality of conductive lines generally extending in a second direction.
Claim 10
Dependent Claim
16 words
The memory array, as set forth in claim 7, wherein said access device comprises a diode.
Claim 11
Dependent Claim
38 words
The memory array, as set forth in claim 8, wherein said diode comprises: a layer of N doped polysilicon disposed on said substrate; and a layer of P+ doped polysilicon disposed on said layer of N doped polysilicon.
Claim 12
Dependent Claim
18 words
The memory array, as set forth in claim 7, wherein said structure changing material comprises a chalcogenide material.
Claim 13
Dependent Claim
40 words
The memory array, as set forth in claim 7, wherein each memory cell further comprises a layer of insulative material substantially surrounding said access device, said layer of dielectric material, said layer of structure changing material, and said second electrode.
Claim 14
Dependent Claim
21 words
The memory array, as set forth in claim 7, wherein said layer of structure changing material is disposed in said pore.
Claim 15
Dependent Claim
26 words
The memory array, as set forth in claim 7, wherein said plurality of memory cells are arranged in a plurality of generally perpendicular rows and columns.
Claim 16
Dependent Claim
60 words
The memory array, as set forth in claim 13, wherein each of said first plurality of conductive lines are coupled to respective memory cells of the plurality of memory cells in a respective row, and wherein each of said second plurality of conductive lines are coupled to respective memory cells of the plurality of memory cells in a respective column.
Claim 17
Dependent Claim
179 words
A memory cell comprising: an access device formed on a semiconductor substrate; a layer of dielectric material disposed on said access device, said layer of dielectric material having a pore therein, said pore being formed by forming a mask over said layer of dielectric material, said mask having a window therein exposing a first portion of said layer of dielectric material, said window being sized at said photolithographic limit, forming a spacer within said window, said spacer covering a peripheral portion of said exposed first portion of said layer of dielectric material to create a second window exposing a second portion of said layer of dielectric material smaller than said photolithographic limit, and removing said exposed second portion of said layer of dielectric material created by said second window to create said pore; a first layer of conductive material disposed within said pore to form a first electrode; a layer of structure changing material disposed on said first electrode; and a second layer of conductive material disposed on said layer of structure changing material to form a second electrode.
Claim 18
Dependent Claim
179 words
A memory cell comprising: an access device formed on a semiconductor substrate; a layer of dielectric material disposed on said access device, said layer of dielectric material having a pore therein, said pore being formed by forming a mask over said layer of dielectric material, said mask having a window therein exposing a first portion of said layer of dielectric material, said window being sized at said photolithographic limit, forming a spacer within said window, said spacer covering a peripheral portion of said exposed first portion of said layer of dielectric material to create a second window exposing a second portion of said layer of dielectric material smaller than said photolithographic limit, and removing said exposed second portion of said layer of dielectric material created by said second window to create said pore; a first layer of conductive material disposed within said pore to form a first electrode; a layer of structure changing material disposed on said first electrode; and a second layer of conductive material disposed on said layer of structure changing material to form a second electrode.
References Cited (Backward Citations)
US3423646A
Cited
GB1319388A
Cited
US3796926A
Cited
US4099260A
Cited
US4115872A
Cited
US4194283A
Cited
US4227297A
Cited
US4203123A
Cited
US4174521A
Cited
US4502208A
Cited
US4272562A
Cited
US4458260A
Cited
US4569698A
Cited
EP0117045A2
Cited
JPS60109266A
Cited
US4876668A
Cited
US4892840A
Cited
US4757359A
Cited
US4823181A
Cited
US4876220A
Cited
US4881114A
Cited
US4809044A
Cited
US4804490A
Cited
US5144404A
Cited
US5296716A
Cited
US5166758A
Cited
US5335219A
Cited
US5341328A
Cited
US5536947A
Cited
US5177567A
Cited
US5166096A
Cited
US5359205A
Cited
US5510629A
Cited
US5751012A
Cited
US5789758A
Cited
US5814527A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |