US6122209A
Expired / Lapsed
US
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Method of margin testing programmable interconnect cell
Assignee: Altera Corp
•
Filing: 1999-07-08
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Granted: 2000-09-19
•
Expires: 2019-07-08
Abstract
Abstract A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.
Inventors
- 👤 Christopher J. Pass
- 👤 James D. Sansbury
- 👤 Raminda U. Madurawe
- 👤 John E. Turner
- 👤 Rakesh H. Patel
- 👤 Peter J. Wright
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; H03K19/17704; H03K19/17736; H03K19/1778
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
44 words
A method of margin testing an array of programmable interconnect junction cells comprising: choosing a selected programmable interconnect junction cell to margin test; decoupling other programmable interconnect junction cells from a test node; and evaluating the margin of the selected programmable interconnect junction cell.
Claim 2
Independent Claim
44 words
A method of margin testing an array of programmable interconnect junction cells comprising: choosing a selected programmable interconnect junction cell to margin test; decoupling other programmable interconnect junction cells from a test node; and evaluating the margin of the selected programmable interconnect junction cell.
Claim 3
Dependent Claim
36 words
The method of claim 1 wherein the evaluating step comprises: exercising a program device of the selected programmable interconnect junction cell to determine a margin of an interconnect element of the selected programmable interconnect junction cell.
Claim 4
Dependent Claim
39 words
The method of claim 1 wherein the evaluating step comprises: determining an impedance of a program device of the selected programmable interconnect junction cell to determine a margin of an interconnect element of the selected programmable interconnect junction cell.
Claim 5
Dependent Claim
46 words
The method of claim 1 wherein the evaluating step comprises: sweeping a control gate of the selected programmable interconnect junction cell until a program device of the selected programmable interconnect junction cell conducts current; and detecting the current of the program device at the test node.
Claim 6
Dependent Claim
37 words
The method of claim 2 wherein the decoupling step comprises: turning off a read device of the selected programmable interconnect junction cell, wherein said read device is serially coupled between the test node and the program device.
Claim 7
Dependent Claim
25 words
The method of claim 1 wherein the decoupling step comprises: supplying a negative voltage to control gate nodes of the other programmable interconnect junction cells.
Claim 8
Dependent Claim
22 words
The method of claim 1 wherein the decoupling step comprises: back biasing a substrate connection of the other programmable interconnect junction cells.
Claim 9
Dependent Claim
53 words
The method of claim 1 wherein evaluating comprises: sweeping a voltage at a control gate of the selected programmable interconnect junction cell until a program device stops conducting current; and using the voltage at which the program device stops conducting as a measure of the margin of the selected programmable interconnect junction cell.
Claim 10
Dependent Claim
99 words
The method of claim 1 wherein the selected programmable interconnect cell is formed by a method comprising: providing a floating gate of a memory cell; providing a tunnel diode of the memory cell; providing a tunnel dielectric of the memory cell to transfer electrons between the tunnel diode and the floating gate; providing a margin device of the memory cell to permit evaluation of a programming margin of the memory cell; and providing a switch coupled between a first conductor and a second conductor, wherein the floating gate of the memory cell is a control node of the switch.
Claim 11
Dependent Claim
53 words
The method of claim 9 further comprising: providing a memory transistor where the floating gate is a control node of the memory transistor; serially coupling the margin device and memory transistor between a drain line and a source line; and controlling the margin device to isolate the drain line from the memory transistor.
Claim 12
Dependent Claim
90 words
The method of claim 1 wherein the selected programmable interconnect cell is formed by a method comprising: providing a first interconnect line; providing a second interconnect line; providing an interconnect element to programmably couple the first interconnect line to the second interconnect line; providing a floating gate to programmably control the interconnect element; and providing a margin device coupled to permit evaluation of a programming margin of the floating gate, wherein the selected interconnect element is a first transistor and the floating gate is a gate of the first transistor.
Claim 13
Dependent Claim
14 words
The method of claim 11 wherein the selected interconnect element is an NMOS transistor.
Claim 14
Dependent Claim
97 words
The method of claim 1 wherein the selected programmable interconnect cell is formed by a method comprising: providing a floating gate; providing a row-line conductor; providing in a first active region, a switch transistor formed by the floating gate, wherein the floating gate programmably couples a first node of the switch transistor and a second node of the switch transistor; and providing in a second active region, a read transistor formed by the row-line conductor; and providing in the second active region, a program transistor formed by the floating gate and serially coupled to the read transistor.
Claim 15
Dependent Claim
22 words
The method of claim 13 further comprising: providing in a third active region, a control gate capacitor coupled to the floating gate.
Claim 16
Dependent Claim
41 words
The method of claim 14 further comprising: providing in the third active region, a tunnel diode beneath a tunnel dielectric and the floating gate; and permitting charge to transfer between the tunnel diode and the floating gate through the tunnel dielection.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-19 | 2004-03-20 | 2004-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-19 | 2008-03-20 | 2008-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-19 | 2012-03-20 | 2012-09-19 | $7700.00 | Window Closed / Lapsed |