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US6144604A
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Simultaneous addressing using single-port RAMs
Assignee: Qualcomm Inc
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Filing: 1999-11-12
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Granted: 2000-11-07
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Expires: 2019-11-12
Abstract
Abstract A read/write electronic memory bank 10, including a plurality of memory units 22-28 and 12-18 which receive a common clock signal having a repetitive clock cycle and have a common input port 20, 21 and a common output port 30, 31. The units function such that in each clock cycle an input word is written to the memory bank 10 from the input port 20, 21 and an output word is read from the memory bank 10 to the output port 30, 31. Each memory unit 22-28 and 12-18 includes a single-port random-access memory (RAM) device 22-28 and a first-in first-out (FIFO) buffer 12-18, such that when the output word is to be read from the same memory unit 22-28 and 12-18 to which the input word is to be written in a given clock cycle, one of the input and output words is passed between the respective port 20, 21, 30, 31 of the memory bank 10 and the FIFO buffer 12-18, instead of between the respective port 20, 21, 30, 31 of the memory bank 10 and the RAM device 22-28.
Inventors
- 👤 Haggai Haim Haller
- 👤 Elisha John Ulmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:20
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
148 words
A read/write electronic memory bank, comprising a plurality of memory units, which receive a common clock signal having a repetitive clock cycle and have a common input port and a common output port, such that in each clock cycle an input word is written to the memory bank from the input port and an output word is read from the memory bank to the output port, each memory unit comprising: a) a single-port random-access memory (RAM) device; and b) a first-in first-out (FIFO) buffer, such that when the output word is to be read from the same memory unit to which the input word is to be written in a given clock cycle, one of the input and output words is passed between the respective port of the memory bank and the FIFO buffer, instead of between the respective port of the memory bank and the RAM device.
Claim 2
Dependent Claim
148 words
A read/write electronic memory bank, comprising a plurality of memory units, which receive a common clock signal having a repetitive clock cycle and have a common input port and a common output port, such that in each clock cycle an input word is written to the memory bank from the input port and an output word is read from the memory bank to the output port, each memory unit comprising: a) a single-port random-access memory (RAM) device; and b) a first-in first-out (FIFO) buffer, such that when the output word is to be read from the same memory unit to which the input word is to be written in a given clock cycle, one of the input and output words is passed between the respective port of the memory bank and the FIFO buffer, instead of between the respective port of the memory bank and the RAM device.
Claim 3
Dependent Claim
78 words
A memory bank according to claim 1, wherein the RAM of each memory unit is coupled directly to the output port, and the FIFO of each memory unit is coupled directly to the input port, so that when the output word is to be read from the same memory unit to which the input word is to be written in the given clock cycle, the input word is held in the respective FIFO until a subsequent clock cycle.
Claim 4
Dependent Claim
74 words
A memory bank according to claim 2, and comprising a controller which checks if the output word is to be read from the same memory unit to which the input word is to be written in each clock cycle, and which allows the input word to be written from the respective FIFO to the RAM of the memory unit on a clock cycle at which the output word is not read from the unit.
Claim 5
Dependent Claim
22 words
A memory bank according to claim 1, wherein each memory unit is assigned a unique allocation of memory addresses in the bank.
Claim 6
Dependent Claim
36 words
A memory bank according to claim 4, wherein the plurality of memory units comprise four memory units, and wherein the memory addresses are allocated among the four units according to two preselected bits of the addresses.
Claim 7
Dependent Claim
46 words
A memory bank according to claim 1, wherein the FIFO buffers have a depth equal to a maximum number of output words that can be read in succession from a single one of the memory units in a system in which the memory bank is used.
Claim 8
Dependent Claim
47 words
A memory bank according to claim 1, wherein the number of memory units and, for each memory unit, sizes of the FIFO and of the RAM are selected responsive to a simulation of the requirements of an application in which the memory bank is to be used.
Claim 9
Independent Claim
143 words
A method for storing data in a memory bank and recalling the stored data therefrom, comprising: a) providing a plurality of memory units each comprising a single-port random-access memory (RAM) device and a first-in first-out (FIFO) buffer coupled to the RAM device; b) driving the plurality of memory units with a clock producing a sequence of clock cycles; c) reading a read word from one of the memory units on each of the clock cycles; and d) writing a write word to one of the memory units on each of the clock cycles, such that when the reading and writing occur to the same memory unit on a common one of the clock cycles, one of the read and write words is passed through the FIFO buffer of the memory unit rather than directly to or from the RAM device of the unit.
Claim 10
Independent Claim
143 words
A method for storing data in a memory bank and recalling the stored data therefrom, comprising: a) providing a plurality of memory units each comprising a single-port random-access memory (RAM) device and a first-in first-out (FIFO) buffer coupled to the RAM device; b) driving the plurality of memory units with a clock producing a sequence of clock cycles; c) reading a read word from one of the memory units on each of the clock cycles; and d) writing a write word to one of the memory units on each of the clock cycles, such that when the reading and writing occur to the same memory unit on a common one of the clock cycles, one of the read and write words is passed through the FIFO buffer of the memory unit rather than directly to or from the RAM device of the unit.
Claim 11
Dependent Claim
59 words
A method according to claim 8, wherein reading the read word from the one of the memory units comprises reading the read word from the RAM comprised in one of the units, and wherein writing the write word to the one of the memory units comprises writing the write word to the FIFO comprised in one of the units.
Claim 12
Dependent Claim
53 words
A method according to claim 9, wherein when the reading and writing occur to the same memory unit on the common one of the clock cycles, writing the write word comprises holding the write word in the FIFO until a subsequent clock cycle on which the reading occurs from a different memory unit.
Claim 13
Dependent Claim
55 words
A method according to claim 9, and comprising checking if the output word is to be read from the same memory unit to which the input word is to be written, and writing the write word directly from the FIFO to the RAM if the output word is to be read from another memory unit.
Claim 14
Dependent Claim
26 words
A method according to claim 8, wherein providing the plurality of memory units comprises assigning each unit a unique allocation of memory addresses in the bank.
Claim 15
Dependent Claim
37 words
A method according to claim 12, wherein providing the plurality of memory units comprises providing four memory units, and wherein the memory addresses are allocated among the four units according to two preselected bits of the addresses.
Claim 16
Dependent Claim
48 words
A method according to claim 8, wherein providing the plurality of memory units comprises determining a depth of the FIFO buffers responsive to the number of times a single one of the units can be accessed in succession in a system in which the memory bank is used.
Claim 17
Dependent Claim
52 words
A method according to claim 8, wherein providing the plurality of memory units comprises selecting the number of memory units and, for each memory unit, sizes of the FIFO and of the RAM, responsive to a simulation of the requirements of an application in which the memory bank is to be used.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-07 | 2004-05-08 | 2004-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-07 | 2008-05-08 | 2008-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-07 | 2012-05-08 | 2012-11-07 | $7700.00 | Window Closed / Lapsed |