Read-only memory and read-only memory devices

Claim 1

An electrically addressable non-volatile read-only memory, comprising: a plurality of memory cells ( 5 ) which in a write operation comprising a part of the manufacturing process of the read-only memory, permanently each are assigned one or two or more logic states according to a determined protocol which in the memory defines permanently written or stored data, and a passive matrix of electrical conductors ( 2 , 4 ) for the addressing; wherein the passive electrical conductor matrix comprises a first and a second electrode structure in respective mutually spaced apart and parallel planes and with parallel electrodes ( 2 , 4 ) in each plane and provided such that the electrodes form a substantially orthogonal x,y matrix; wherein the electrodes ( 2 ) in the first electrode structure comprise the columns of the matrix or x electrodes and the electrodes ( 4 ) in the second electrode structure comprise the rows of the matrix or y electrodes; wherein at least a portion of the volume between the intersection of an x electrode ( 2 ) and a y electrode ( 4 ) defines a memory cell ( 5 ) in the read-only memory; wherein are provided at least one semiconductor material ( 9 ) with rectifying properties in relation to a selected electrical conducting electrode material and a first electrical isolating material ( 6 ); wherein the semiconductor material ( 9 ) in electrical contact with an electrode ( 2 , 4 ) in the memory cell forms a diode junction in the interface between semiconductor material and electrode material; wherein a logic state in each case is given by the impedance value of the memory cell ( 5 ), said impedance value substantially being given by either the impedance characteristics of the semiconductor material or the impedance characteristics of the isolating material, and the impedance characteristic of the diode junction; characterized in that the y electrodes ( 4 ) are provided on a second electrical isolating material ( 12 ) which is realized as strip-like structures of substantially same form and extension as the y electrodes ( 4 ) and provided adjacent to the x electrodes ( 2 ) as part of the matrix, that the semiconductor material is provided over the electrode structures, a contact area ( 11 ) in the memory cell ( 5 ) thus being defined by the portions which respectively extend along each side edge of the y electrode ( 4 ) where it overlaps the x electrode ( 2 ) in the memory cell ( 5 ), that a first logic state of a memory cell ( 5 ) in the read-only memory is generated by an active portion of the semiconductor material ( 9 ) covering the whole contact area ( 11 ) in the memory cell, the diode junction thus comprising the whole contact area of the memory cell, that a second logic state in a selected memory cell ( 5 ) in the read-only memory is generated by both electrode structures in the memory cell being covered by the first isolating material ( 6 ), that one or more additional logic states in a memory cell ( 5 ) in the read-only memory is generated by an active portion of the semiconductor material ( 9 ) covering only a part of the contact area ( 11 ), such that the data which are stored in the memory may be represented by the logic states in a binary or multi-valued code, and that said one or more additionally logic states are given by impedance values determined by the extension of the active portion of the semiconductor material, and the extension of the part of the contact area which forms the diode junction; and that a logic state in each case is given by the impedance value of the memory cell ( 5 ), said impedance value substantially being given by one or more of the following factors: the impedance characteristics of the semiconductor material, the impedance characteristics of the isolating material, the extension of the active portion of the semiconductor material, the extension of the part of the contact area which forms the diode junction, and the impedance characteristic of the diode junction.