Patent US6512401B2 successfully refreshed from Google Patents.
US6512401B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output buffer for high and low voltage bus
Assignee: Intel Corp
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Filing: 1999-09-10
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Granted: 2003-01-28
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Expires: 2019-09-10
Abstract
Abstract Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the circuit configurations. The respective circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.
Inventors
- 👤 Lawrence T. Clark
- 👤 Thomas J. Mozdzen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
147 words
A multiple drive voltage level output buffer comprising: a plurality of thick gate MOS transistors coupled in a circuit configuration; said plurality including as pull-up transistors, at least a thick gate P-channel MOS (PMOS) transistor and a thick gate N-channel MOS (NMOS) transistor, both respectively coupled between separate voltage supply voltage level ports and an output port of said output buffer; said plurality further including as pull-down transistors, at least two more thick gate NMOS transistors, both respectively coupled between ground and said output port; wherein at least one of said pull-up transistors and one of said pull-down transistors being coupled in said circuit configuration to be driven on hard and provide a high voltage swing; and wherein another of said pull-up transistors and one of said pull-down transistors being coupled in said circuit configuration to be driven on less hard and provide a reduced voltage swing.
Claim 2
Dependent Claim
147 words
A multiple drive voltage level output buffer comprising: a plurality of thick gate MOS transistors coupled in a circuit configuration; said plurality including as pull-up transistors, at least a thick gate P-channel MOS (PMOS) transistor and a thick gate N-channel MOS (NMOS) transistor, both respectively coupled between separate voltage supply voltage level ports and an output port of said output buffer; said plurality further including as pull-down transistors, at least two more thick gate NMOS transistors, both respectively coupled between ground and said output port; wherein at least one of said pull-up transistors and one of said pull-down transistors being coupled in said circuit configuration to be driven on hard and provide a high voltage swing; and wherein another of said pull-up transistors and one of said pull-down transistors being coupled in said circuit configuration to be driven on less hard and provide a reduced voltage swing.
Claim 3
Dependent Claim
39 words
The multiple drive voltage level output buffer of claim 1 , wherein at least one of the pull-up and pull-down transistors comprise a plurality of transistors coupled so as to emulate a transistor having approximately a particular transistor width.
Claim 4
Dependent Claim
63 words
The multiple drive voltage level output buffer of claim 2 , wherein a first of said pull-up transistors and a first of said pull-down transistors are specifically adapted to provide better electrical performance than a second of said pull-up transistors and a second of said pull-down transistors for a specific mode of operation that depends, at least in part, voltage supply voltage level.
Claim 5
Dependent Claim
51 words
The multiple drive voltage level output buffer of claim 3 , wherein the thick gate PMOS pull-up transistor is coupled to be driven on hard during high voltage mode circuit operation and the thick gate NMOS pull-up transistor is coupled to driven on less hard during low voltage mode circuit operation.
Claim 6
Dependent Claim
37 words
The multiple drive voltage level output buffer of claim 3 , wherein the thick gate PMOS pull-up transistor and the thick gate NMOS pull-up transistor are coupled to be driven on during high voltage mode circuit operation.
Claim 7
Dependent Claim
29 words
The multiple threshold voltage level output buffer of claim 3 , wherein both thick gate NMOS pull-down transistors are coupled to be driven on during high voltage mode operation.
Claim 8
Dependent Claim
34 words
The multiple threshold voltage level output buffer of claim 3 , wherein at least one of the thick gate NMOS pull-down transistors is coupled to be driven on hard during high voltage mode operation.
Claim 9
Dependent Claim
33 words
The multiple threshold voltage level output buffer of claim 7 , wherein at least one of the thick gate NMOS pull-down transistors is coupled to be driven on less hard during low voltage
References Cited (Backward Citations)
US4038564A
Cited
US4408135A
Cited
US4731553A
Cited
US4853560A
Cited
US4853560B1
Cited
US5097152A
Cited
US5095230A
Cited
US5341045A
Cited
US5399918A
Cited
US5811991A
Cited
EP0789459A1
Cited
US5830795A
Cited
US5739700A
Cited
US6043683A
Cited
US5748303A
Cited
US5894238A
Cited
US5914618A
Cited
US6040592A
Cited
US6057586A
Cited
US6133563A
Cited
US5859450A
Cited
US6118482A
Cited
US5939936A
Cited
US6144330A
Cited
US6133749A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-01-27 | 2006-07-29 | 2007-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-01-27 | 2010-07-29 | 2011-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-01-27 | 2014-07-29 | 2015-01-28 | $7700.00 | Window Closed / Lapsed |