US6597609B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile memory with test rows for disturb detection
Assignee: Micron Technology Inc
•
Filing: 2001-08-30
•
Granted: 2003-07-22
•
Expires: 2021-08-30
Abstract
Abstract A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not externally accessible for standard program and read operations. The test rows are located near bit line driver circuitry to insure the highest exposure to bit line voltages that may disturb memory cells in the array.
Inventors
- 👤 Christophe J. Chevallier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 03:46
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3427; G11C16/3436; G11C16/344; G11C16/3445; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24; G11C29/52; G11C16/04
Claims Analysis
Total Claims: 50
Claim 1
Independent Claim
87 words
A non-volatile memory device comprising: an array of reprogrammable non-volatile memory cells arranged in rows and columns; a plurality of bit lines coupled to the non-volatile memory cells; a driver circuit coupled to the plurality of bit lines; and test rows coupled to the array, wherein the driver circuit comprises first and second bit line drivers located at opposite ends of the array rows, and the test rows comprise first and second pairs of test rows respectively located adjacent to the first and second bit line drivers.
Claim 2
Dependent Claim
87 words
A non-volatile memory device comprising: an array of reprogrammable non-volatile memory cells arranged in rows and columns; a plurality of bit lines coupled to the non-volatile memory cells; a driver circuit coupled to the plurality of bit lines; and test rows coupled to the array, wherein the driver circuit comprises first and second bit line drivers located at opposite ends of the array rows, and the test rows comprise first and second pairs of test rows respectively located adjacent to the first and second bit line drivers.
Claim 3
Dependent Claim
16 words
The non-volatile memory device of claim 1 wherein the non-volatile memory cells are floating gate transistors.
Claim 4
Dependent Claim
85 words
A flash memory device comprising: an array of floating gate non-volatile memory cells arranged in rows and columns; a bit line coupled to the non-volatile memory cells; first and second driver circuits respectively coupled to first and second end regions of the bit line; a decoder circuit to selectively couple the first and second driver circuits to the bit line; and first and second sets of addressable memory cell test rows coupled to the array and respectively located near the first and second driver circuits.
Claim 5
Dependent Claim
85 words
A flash memory device comprising: an array of floating gate non-volatile memory cells arranged in rows and columns; a bit line coupled to the non-volatile memory cells; first and second driver circuits respectively coupled to first and second end regions of the bit line; a decoder circuit to selectively couple the first and second driver circuits to the bit line; and first and second sets of addressable memory cell test rows coupled to the array and respectively located near the first and second driver circuits.
Claim 6
Dependent Claim
22 words
The flash memory device of claim 3 wherein the first and second sets of addressable test rows each comprise two test rows.
Claim 7
Dependent Claim
34 words
The flash memory device of claim 3 further comprising a disturb test circuit to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.
Claim 8
Dependent Claim
80 words
A non-volatile memory device comprising: an array of non-volatile memory cells arranged in rows and columns; a bit line having a resistance of R and coupled to the non-volatile memory cells; X distributed driver circuits coupled to the bit line; and X pairs of addressable test rows coupled to the array and respectively located near the X driver circuits, wherein X equals two and the two pairs of addressable test rows are located at opposite ends of the bit line.
Claim 9
Dependent Claim
80 words
A non-volatile memory device comprising: an array of non-volatile memory cells arranged in rows and columns; a bit line having a resistance of R and coupled to the non-volatile memory cells; X distributed driver circuits coupled to the bit line; and X pairs of addressable test rows coupled to the array and respectively located near the X driver circuits, wherein X equals two and the two pairs of addressable test rows are located at opposite ends of the bit line.
Claim 10
Independent Claim
64 words
A method of erasing memory cells in a non-volatile memory device comprising: initiating an erase operation on memory cells located in a first part of an addressable array of memory cells; and performing a disturb test operation on test rows to forecast a lack of memory cell disturb during the erase operation of memory cells located in a second part of the addressable array.
Claim 11
Independent Claim
64 words
A method of erasing memory cells in a non-volatile memory device comprising: initiating an erase operation on memory cells located in a first part of an addressable array of memory cells; and performing a disturb test operation on test rows to forecast a lack of memory cell disturb during the erase operation of memory cells located in a second part of the addressable array.
Claim 12
Dependent Claim
47 words
The method of claim 7 wherein performing the disturb test operation comprises: coupling a predefined word line voltage to memory cells located in the test rows; and determining if the memory cells located in the test rows are activated in response to the predefined word line voltage.
Claim 13
Dependent Claim
35 words
The method of claim 7 further comprises performing a data recovery operation on the memory cells located in the second part of the addressable array based upon the disturb test operation on the test rows.
Claim 14
Dependent Claim
31 words
The method of claim 7 further comprises performing a data recovery operation on the memory cells located in the test rows based upon the disturb test operation on the test rows.
Claim 15
Dependent Claim
23 words
The method of claim 7 wherein the test rows comprise two test rows located on an edge of addressable array of memory cells.
Claim 16
Dependent Claim
15 words
The method of claim 7 wherein the memory cells are floating gate transistor memory cells.
Claim 17
Dependent Claim
17 words
The method of claim 7 further comprising: locating the test rows near at least one driver circuit.
Claim 18
Independent Claim
78 words
A method of operating a non-volatile memory device comprising: initiating an erase operation on a first erase block of memory cells located in an addressable array of memory cells, wherein the array has X erase blocks; and performing a disturb test operation on test rows to forecast a lack of memory cell disturb during the erase operation of memory cells located in remaining X−1 erasable blocks, wherein the test rows are not located within the X erase blocks.
Claim 19
Independent Claim
78 words
A method of operating a non-volatile memory device comprising: initiating an erase operation on a first erase block of memory cells located in an addressable array of memory cells, wherein the array has X erase blocks; and performing a disturb test operation on test rows to forecast a lack of memory cell disturb during the erase operation of memory cells located in remaining X−1 erasable blocks, wherein the test rows are not located within the X erase blocks.
Claim 20
Dependent Claim
22 words
The method of claim 14 wherein the test rows comprise two test rows located on an edge of the X erase blocks.
Claim 21
Dependent Claim
28 words
The method of claim 14 further comprises performing a data recovery operation on the remaining X−1 erasable blocks based upon the disturb test operation on the test rows.
Claim 22
Dependent Claim
15 words
The method of claim 14 wherein the memory cells are floating gate transistor memory cells.
Claim 23
Dependent Claim
17 words
The method of claim 14 further comprising: locating the test rows near at least one driver circuit.
Claim 24
Independent Claim
97 words
A method of operating a non-volatile memory system comprising: initiating an erase operation on memory cells located in a first block of an array of memory cells of a memory device in response to instructions from an external processor; performing a disturb test operation on test rows to forecast a lack of memory cell disturb during the erase operation or a prior operation of memory cells located in additional blocks of the array; and performing a data recovery operation on the memory cells located in the additional blocks of the array based upon the disturb test operation.
Claim 25
Independent Claim
97 words
A method of operating a non-volatile memory system comprising: initiating an erase operation on memory cells located in a first block of an array of memory cells of a memory device in response to instructions from an external processor; performing a disturb test operation on test rows to forecast a lack of memory cell disturb during the erase operation or a prior operation of memory cells located in additional blocks of the array; and performing a data recovery operation on the memory cells located in the additional blocks of the array based upon the disturb test operation.
Claim 26
Dependent Claim
23 words
The method of claim 19 wherein the test rows comprise two test rows located on an edge of the array of memory cells.
Claim 27
Dependent Claim
15 words
The method of claim 19 wherein the memory cells are floating gate transistor memory cells.
Claim 28
Dependent Claim
17 words
The method of claim 19 further comprising: locating the test rows near at least one driver circuit.
Claim 29
Dependent Claim
97 words
A memory system comprising: a processor; and a non-volatile memory device coupled to the processor and comprising, an array of floating gate non-volatile memory cells arranged in rows and columns, a bit line coupled to the non-volatile memory cells, first and second driver circuits respectively coupled to first and second end regions of the bit line, a decoder circuit to selectively couple the first and second driver circuits to the bit line, and first and second sets of addressable memory cell test rows coupled to the array and respectively located near the first and second driver circuits.
Claim 30
Dependent Claim
97 words
A memory system comprising: a processor; and a non-volatile memory device coupled to the processor and comprising, an array of floating gate non-volatile memory cells arranged in rows and columns, a bit line coupled to the non-volatile memory cells, first and second driver circuits respectively coupled to first and second end regions of the bit line, a decoder circuit to selectively couple the first and second driver circuits to the bit line, and first and second sets of addressable memory cell test rows coupled to the array and respectively located near the first and second driver circuits.
Claim 31
Dependent Claim
21 words
The memory system of claim 23 wherein the first and second sets of addressable test rows each comprise two test rows.
Claim 32
Dependent Claim
38 words
The memory system of claim 23 further comprising a disturb test circuit coupled to the test rows to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.
Claim 33
Dependent Claim
78 words
A memory device comprising: an array of memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; and first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits, wherein the first and second driver circuits are located at opposite ends of the plurality of bit lines.
Claim 34
Dependent Claim
78 words
A memory device comprising: an array of memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; and first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits, wherein the first and second driver circuits are located at opposite ends of the plurality of bit lines.
Claim 35
Dependent Claim
80 words
A memory device comprising: an array of reprogrammable memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and wherein the first and second driver circuits are activated simultaneously to drive data on the plurality of bit lines.
Claim 36
Dependent Claim
80 words
A memory device comprising: an array of reprogrammable memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and wherein the first and second driver circuits are activated simultaneously to drive data on the plurality of bit lines.
Claim 37
Dependent Claim
80 words
A memory device comprising: an array of reprogrammable memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and wherein the first and second driver circuits are independently activated to drive data on the plurality of bit lines.
Claim 38
Dependent Claim
80 words
A memory device comprising: an array of reprogrammable memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and wherein the first and second driver circuits are independently activated to drive data on the plurality of bit lines.
Claim 39
Dependent Claim
91 words
A memory device comprising: an array of memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; and first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits, wherein the first and second driver circuits are independently activated to drive data on the plurality of bit lines and wherein an un-activated driver circuit is placed in a tri-state condition.
Claim 40
Dependent Claim
91 words
A memory device comprising: an array of memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; and first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits, wherein the first and second driver circuits are independently activated to drive data on the plurality of bit lines and wherein an un-activated driver circuit is placed in a tri-state condition.
Claim 41
Dependent Claim
96 words
A memory device comprising: an array of memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; and first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits, further comprising a disturb circuit coupled to the first and second sets of test rows to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.
Claim 42
Dependent Claim
96 words
A memory device comprising: an array of memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; and first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits, further comprising a disturb circuit coupled to the first and second sets of test rows to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.
Claim 43
Dependent Claim
91 words
A memory device comprising: an array of reprogrammable memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; a third driver circuit electrically coupleable to the plurality of bit lines; and a third set of test rows coupled to the array and respectively located near the third driver circuit.
Claim 44
Dependent Claim
91 words
A memory device comprising: an array of reprogrammable memory cells arranged in rows and columns; a plurality of bit lines coupled to the memory cells; a first and second driver circuits electrically coupleable to the plurality of bit lines; first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; a third driver circuit electrically coupleable to the plurality of bit lines; and a third set of test rows coupled to the array and respectively located near the third driver circuit.
Claim 45
Dependent Claim
67 words
A non-volatile memory device comprising: an array of non-volatile memory cells arranged in rows and columns; a plurality of bit lines coupled to the non-volatile memory cells; a driver circuit coupled to the plurality of bit lines; test rows coupled to the array and located near the driver circuit; and a disturb test circuit to determine if the memory cells of the test rows have been disturbed.
Claim 46
Dependent Claim
67 words
A non-volatile memory device comprising: an array of non-volatile memory cells arranged in rows and columns; a plurality of bit lines coupled to the non-volatile memory cells; a driver circuit coupled to the plurality of bit lines; test rows coupled to the array and located near the driver circuit; and a disturb test circuit to determine if the memory cells of the test rows have been disturbed.
Claim 47
Dependent Claim
110 words
A flash memory device comprising: an array of floating gate non-volatile memory cells arranged in rows and columns; a bit line coupled to the non-volatile memory cells; first and second driver circuits respectively coupled to first and second end regions of the bit line; a decoder circuit to selectively couple the first and second driver circuits to the bit line; first and second sets of addressable memory cell test rows coupled to the array and respectively located near the first and second driver circuits; and a disturb test circuit to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.
Claim 48
Dependent Claim
110 words
A flash memory device comprising: an array of floating gate non-volatile memory cells arranged in rows and columns; a bit line coupled to the non-volatile memory cells; first and second driver circuits respectively coupled to first and second end regions of the bit line; a decoder circuit to selectively couple the first and second driver circuits to the bit line; first and second sets of addressable memory cell test rows coupled to the array and respectively located near the first and second driver circuits; and a disturb test circuit to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.
Claim 49
Dependent Claim
80 words
A non-volatile memory device comprising: an array of non-volatile memory cells arranged in rows and columns; a bit line having a resistance of R and coupled to the non-volatile memory cells; X distributed driver circuits coupled to the bit line; X pairs of addressable test rows coupled to the array and respectively located near the X driver circuits; and a disturb test circuit to determine if the memory cells of the X pairs of addressable test rows have been disturbed.
Claim 50
Dependent Claim
80 words
A non-volatile memory device comprising: an array of non-volatile memory cells arranged in rows and columns; a bit line having a resistance of R and coupled to the non-volatile memory cells; X distributed driver circuits coupled to the bit line; X pairs of addressable test rows coupled to the array and respectively located near the X driver circuits; and a disturb test circuit to determine if the memory cells of the X pairs of addressable test rows have been disturbed.
References Cited (Backward Citations)
US6459623B1
Cited
US5572692A
Cited
US5487044A
Cited
US5490110A
Cited
US5299147A
Cited
US5627838A
Cited
US5644530A
Cited
US5617350A
Cited
US5671176A
Cited
US5963473A
Cited
US5715193A
Cited
US5818757A
Cited
US5912837A
Cited
US5838040A
Cited
US5991213A
Cited
US5896316A
Cited
US6078534A
Cited
US5981340A
Cited
US5920501A
Cited
US6061270A
Cited
US6101150A
Cited
US6285608B1
Cited
US6026018A
Cited
US5991202A
Cited
US6058060A
Cited
US6285593B1
Cited
US6108240A
Cited
US6181599B1
Cited
US6285592B1
Cited
US6222761B1
Cited
US6407953B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-07-21 | 2007-01-20 | 2007-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-07-21 | 2011-01-20 | 2011-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-07-21 | 2015-01-20 | 2015-07-22 | $7700.00 | Window Closed / Lapsed |