Method and apparatus for using supply voltage for testing in semiconductor memory devices

Claim 2

A bitline driver circuit, suitable for receiving a supply signal and a programming signal and providing an output over a data line, the bitline driver circuit comprising: a logic circuit suitable for receiving an input; a supply switch selectively activated by the logic circuit, the supply switch coupling the supply signal to the data line; and a program switch coupled between the programming signal and the data line wherein the logic circuit operates the program switch to generally isolate the programming signal from the data line when the supply switch is activated.

Claim 3

The bitline driver circuit of claim 1 wherein the input includes one of a plurality of quadprogramming signal values and one of a plurality of bitline data signal values.

Claim 4

The bitline driver circuit of claim 2 wherein the supply switch is selectively activated in response to a predetermined combination of the quadprogramming and bitline data signal values.

Claim 5

A bitline driver circuit suitable for receiving a supply signal, a programming signal, and a logic input, and providing and output, the bitline driver circuit comprising: a data line for providing the output; a logic circuit suitable for receiving the logic input and providing a first logic output and a second logic output; a general-mode circuit comprising: a first level shifter receiving the programming signal and the first logic output and providing a first-level output; and a programming switch operably coupling the programming signal to the data line and selectively activated by the first-level output; and a test-mode circuit comprising: a second level shifter receiving the second logic output and providing a second-level output; and a supply switch operably coupling the supply signal to the data line and selectively activated by the second-level output; wherein the programming switch generally isolates the programming signal from the data line when the supply switch is activated.

Claim 6

A bitline driver circuit suitable for receiving a supply signal, a programming signal, and a logic input, and providing and output, the bitline driver circuit comprising: a data line for providing the output; a logic circuit suitable for receiving the logic input and providing a first logic output and a second logic output; a general-mode circuit comprising: a first level shifter receiving the programming signal and the first logic output and providing a first-level output; and a programming switch operably coupling the programming signal to the data line and selectively activated by the first-level output; and a test-mode circuit comprising: a second level shifter receiving the second logic output and providing a second-level output; and a supply switch operably coupling the supply signal to the data line and selectively activated by the second-level output; wherein the programming switch generally isolates the programming signal from the data line when the supply switch is activated.

Claim 7

The bitline driver circuit of claim 4 wherein the logic input includes a bitline data signal and a quadprogramming signal, the bitline driver circuit further comprising a grounding switch connected between the data line and a substrate ground, the grounding switch activated by the bitline data signal.

Claim 8

The bitline driver circuit of claim 5 wherein the switches are n-channel transistors.

Claim 9

A memory device bitline driver circuit comprises: a first voltage node that receives a first voltage and a second voltage node that receives a second voltage; first and second transistors coupled respectively between the first and second voltage nodes, and an output node of the bitline driver circuit, wherein the first and second voltage nodes are coupled to first and second positive voltages, respectively; and control circuitry coupled to the first and second transistor for selectively coupling the first or second voltage node to a bitline in response to an operating status of the memory device.

Claim 10

A memory device bitline driver circuit comprises: a first voltage node that receives a first voltage and a second voltage node that receives a second voltage; first and second transistors coupled respectively between the first and second voltage nodes, and an output node of the bitline driver circuit, wherein the first and second voltage nodes are coupled to first and second positive voltages, respectively; and control circuitry coupled to the first and second transistor for selectively coupling the first or second voltage node to a bitline in response to an operating status of the memory device.

Claim 11

A memory device bitline driver circuit comprises: a first voltage node that receives a first voltage and a second voltage node that receives a second voltage; first and second transistors coupled respectively between the first and second voltage nodes, and an output node of the bitline driver circuit; control circuitry coupled to the first and second transistor for selectively coupling the first or second voltage node to a bitline in response to an operating status of the memory device; wherein the control circuitry comprises: first and second level shifters for providing control signals to the gates of the first and second transistors; and logic circuitry for receiving a bitline data signal and a quad programming signal, and providing an output to the first and second level shifters.

Claim 12

A memory device bitline driver circuit comprises: a first voltage node that receives a first voltage and a second voltage node that receives a second voltage; first and second transistors coupled respectively between the first and second voltage nodes, and an output node of the bitline driver circuit; control circuitry coupled to the first and second transistor for selectively coupling the first or second voltage node to a bitline in response to an operating status of the memory device; wherein the control circuitry comprises: first and second level shifters for providing control signals to the gates of the first and second transistors; and logic circuitry for receiving a bitline data signal and a quad programming signal, and providing an output to the first and second level shifters.

Claim 13

The memory device of claim 7, wherein the first and second transistors comprise n-channel transistors.

Claim 14

The memory device of claim 7, wherein the first and second transistors are controlled by activating the first transistor while keeping the second transistor off.

Claim 15

The memory device of claim 7, wherein the first and second transistors are controlled by activating the second transistor while keeping the first transistor off.

Claim 16

A memory device bitline driver circuit comprises: a first voltage node that receives a first voltage and a second voltage node that receives a second voltage; first and second transistors coupled respectively between the first and second voltage nodes, and an output node of the bitline driver circuit; control circuitry coupled to the first and second transistor for selectively coupling the first or second voltage node to a bitline in response to an operating status of the memory device; and wherein the first voltage is selected during normal operation of the bitline driver circuit, and the second voltage is selected during the test operation of the bitline driver circuit.

Claim 17

A memory device bitline driver circuit comprises: a first voltage node that receives a first voltage and a second voltage node that receives a second voltage; first and second transistors coupled respectively between the first and second voltage nodes, and an output node of the bitline driver circuit; control circuitry coupled to the first and second transistor for selectively coupling the first or second voltage node to a bitline in response to an operating status of the memory device; and wherein the first voltage is selected during normal operation of the bitline driver circuit, and the second voltage is selected during the test operation of the bitline driver circuit.

Claim 18

A memory device bitline driver circuit comprising: a first voltage node; a second voltage node; first and second transistors coupled respectively between the first and second voltage nodes, and an output node of the bitline driver circuit, wherein first and second transistors are n-channel transistors, and wherein, the first and second transistors are controlled alternatively and selectively by a logic circuit including: activating a first transistor while keeping a second transistor off, and activating a second transistor while keeping a first transistor off; control circuitry coupled to the first and second transistors for selectively coupling the first or second voltage node to a bitline in response to an operating status of the memory device wherein the first voltage node is selected during normal operation of the bitline driver circuit, and wherein the second voltage node is selected during the test operation of the bitline driver circuit; wherein the control circuitry includes a first and a second level shifter for providing an output to gates of the first and second transistors, and logic circuitry for receiving a bitline data signal and a quad programming signal, and providing an output to the first and second level shifters.

Claim 19

A memory device bitline driver circuit comprising: a first voltage node; a second voltage node; first and second transistors coupled respectively between the first and second voltage nodes, and an output node of the bitline driver circuit, wherein first and second transistors are n-channel transistors, and wherein, the first and second transistors are controlled alternatively and selectively by a logic circuit including: activating a first transistor while keeping a second transistor off, and activating a second transistor while keeping a first transistor off; control circuitry coupled to the first and second transistors for selectively coupling the first or second voltage node to a bitline in response to an operating status of the memory device wherein the first voltage node is selected during normal operation of the bitline driver circuit, and wherein the second voltage node is selected during the test operation of the bitline driver circuit; wherein the control circuitry includes a first and a second level shifter for providing an output to gates of the first and second transistors, and logic circuitry for receiving a bitline data signal and a quad programming signal, and providing an output to the first and second level shifters.

Claim 20

A bitline driver circuit comprising: a logic circuit having a first input node and a second input node for respectively receiving a programming signal and a supply signal, and two output nodes for providing input signals to a first level shifter and a second level shifter; a first transistor coupled to an output of the first level shifter; a second transistor coupled to an output of the second level shifter; a third transistor coupled to the first input node of the logic circuit, and simultaneously coupled to a controlled node of the first transistor and a bitline; a first voltage node and a second voltage node.

Claim 21

A bitline driver circuit comprising: a logic circuit having a first input node and a second input node for respectively receiving a programming signal and a supply signal, and two output nodes for providing input signals to a first level shifter and a second level shifter; a first transistor coupled to an output of the first level shifter; a second transistor coupled to an output of the second level shifter; a third transistor coupled to the first input node of the logic circuit, and simultaneously coupled to a controlled node of the first transistor and a bitline; a first voltage node and a second voltage node.

Claim 22

The bitline driver circuit of claim 14, wherein the second transistor is activated by about 12.0 volts.

Claim 23

The bitline driver circuit of claim 14, wherein the first voltage node and second voltage node are respectively connected to Vpp and a charge pump.

Claim 24

The bitline driver circuit of claim 14, wherein the first voltage node and second voltage node are respectively connected to an analog reference voltage and Vpp.

Claim 25

The bitline driver circuit of claim 14, wherein a third voltage node is connected simultaneously to Vpp and a first voltage node or second voltage node, whichever node is connected to Vpp.

Claim 26

The bitline driver circuit of claim 14, wherein a fourth voltage node is connected to a supply voltage.

Claim 27

The bitline driver circuit of claim 19, wherein the supply voltage is between about 5.5 and 6.0 volts.

Claim 28

The bitline driver circuit of claim 19, wherein the supply voltage provides current to a data line.

Claim 29

The bitline driver circuit of claim 21, wherein the supply voltage is set externally to provide a predetermined amount of voltage to the data line.