US6629220B1 — Method and apparatus for dynamic arbitration betw…

Claim 1

Independent Claim 91 words

A method for arbitrating memory access requests, the method comprising: receiving a first memory access request at a first request queue; dynamically raising the priority of the first request queue over a second request queue if the first memory access request is of a first type; and dynamically raising the priority of the second request queue over the first request queue before all requests of the first type in the first request queue have been serviced in response to a predetermined maximum number of requests of the first type being serviced.

Claim 2

Independent Claim 91 words

A method for arbitrating memory access requests, the method comprising: receiving a first memory access request at a first request queue; dynamically raising the priority of the first request queue over a second request queue if the first memory access request is of a first type; and dynamically raising the priority of the second request queue over the first request queue before all requests of the first type in the first request queue have been serviced in response to a predetermined maximum number of requests of the first type being serviced.

Claim 3

Dependent Claim 31 words

The method of claim 1 further comprising dynamically raising the priority of the first request queue over the second request queue after a request of a second type has been serviced.

Claim 4

Dependent Claim 17 words

The method of claim 2 wherein the first type is isochronous and the second type is asynchronous.

Claim 5

Dependent Claim 37 words

The method of claim 1 further comprising receiving a second memory access request of the first type at the first request queue; and processing the first and second memory access requests in the order they were received.

Claim 6

Dependent Claim 42 words

The method of claim 1 further comprising if the first queue includes a second memory access request of a second type ahead of the first memory access request of the first type, promoting the second memory access request to the first type.

Claim 7

Dependent Claim 18 words

The method of claim 3 further comprising indicating the memory access request type in the memory access request.

Claim 8

Dependent Claim 19 words

The method of claim 2 wherein dynamically raising the priority of the first queue includes dynamically configuring an arbiter.

Claim 9

Dependent Claim 49 words

The method of claim 1 further comprising if a third request queue includes a memory access request of the first type, prioritizing the third request queue above the second request queue and equally with the first request queue if the first memory access request is of the first type.

Claim 10

Independent Claim 80 words

A method for processing memory access requests, the method comprising: dynamically configuring an arbiter to prioritize a first request queue above a second request queue if the first request queue receives a memory access request of a first type; and dynamically configuring the arbiter to prioritize the second request queue before all memory access requests of the first type have been serviced in response to a first predetermined maximum number of memory access requests of the first type being serviced.

Claim 11

Independent Claim 80 words

A method for processing memory access requests, the method comprising: dynamically configuring an arbiter to prioritize a first request queue above a second request queue if the first request queue receives a memory access request of a first type; and dynamically configuring the arbiter to prioritize the second request queue before all memory access requests of the first type have been serviced in response to a first predetermined maximum number of memory access requests of the first type being serviced.

Claim 12

Dependent Claim 62 words

The method of claim 9 further comprising servicing a second predetermined maximum number of memory access requests of a second type from the second request queue when the second request queue is prioritized, and dynamically reconfiguring the first arbiter to reprioritize the first request queue after the second predetermined maximum number of memory access requests of the second type have been serviced.

Claim 13

Independent Claim 71 words

A method for processing memory requests comprising: at each arbitration point in a memory request pipe, dynamically prioritizing a first request queue that includes a memory access request of a first type; and dynamically prioritizing a second request queue over the first request queue before all memory access requests of the first type have been processed in response to a predetermined maximum number of requests of the first type being processed.

Claim 14

Independent Claim 71 words

A method for processing memory requests comprising: at each arbitration point in a memory request pipe, dynamically prioritizing a first request queue that includes a memory access request of a first type; and dynamically prioritizing a second request queue over the first request queue before all memory access requests of the first type have been processed in response to a predetermined maximum number of requests of the first type being processed.

Claim 15

Dependent Claim 62 words

The method of claim 11 further comprising at each point in the request pipe, when all memory access requests of the first type in the prioritized queue have been serviced or the predetermined maximum number of memory access requests corresponding to the arbitration point have been serviced, dynamically prioritizing a request queue that includes a memory access request of a second type.

Claim 16

Dependent Claim 17 words

The method of claim 11 wherein the first type is isochronous and the second type is asynchronous.

Claim 17

Independent Claim 113 words

An apparatus comprising: first and second request queues to receive memory access requests; and a configurable arbiter coupled to the first and second request queues, the configurable arbiter to dynamically raise the priority of the first request queue relative to the priority of the second request queue in response to the first request queue receiving a memory access request of a first type, the configurable arbiter further to dynamically raise the priority of the second request queue relative to the priority of the first request queue before all of the requests of the first type have been serviced in response to a predetermined maximum number of requests of the first type being serviced.

Claim 18

Independent Claim 113 words

An apparatus comprising: first and second request queues to receive memory access requests; and a configurable arbiter coupled to the first and second request queues, the configurable arbiter to dynamically raise the priority of the first request queue relative to the priority of the second request queue in response to the first request queue receiving a memory access request of a first type, the configurable arbiter further to dynamically raise the priority of the second request queue relative to the priority of the first request queue before all of the requests of the first type have been serviced in response to a predetermined maximum number of requests of the first type being serviced.

Claim 19

Dependent Claim 19 words

The apparatus of claim 14 wherein the first type of memory access request is an isochronous memory access request.

Claim 20

Dependent Claim 18 words

The apparatus of claim 14 wherein memory access requests in the first request queue are processed in order.

Claim 21

Dependent Claim 13 words

The apparatus of claim 14 wherein the first predetermined maximum number is programmable.

Claim 22

Dependent Claim 42 words

The apparatus of claim 15 wherein the configurable arbiter is further to dynamically raise the priority of the first request queue relative to the second request queue after a second predetermined number of requests from the second request queue have been serviced.

Claim 23

Dependent Claim 94 words

A memory controller comprising: a first memory access request queue to temporarily store memory access requests of a first high priority request type; a second memory access request queue to temporarily store memory access requests of a second lower priority request type; and a first configurable arbiter coupled to the first and second memory access request queues, the first configurable arbiter to dynamically prioritize the first memory access request queue above the second memory access request queue until a first predetermined maximum number of memory access requests of the first type have been serviced.

Claim 24

Dependent Claim 94 words

A memory controller comprising: a first memory access request queue to temporarily store memory access requests of a first high priority request type; a second memory access request queue to temporarily store memory access requests of a second lower priority request type; and a first configurable arbiter coupled to the first and second memory access request queues, the first configurable arbiter to dynamically prioritize the first memory access request queue above the second memory access request queue until a first predetermined maximum number of memory access requests of the first type have been serviced.

Claim 25

Dependent Claim 24 words

The memory controller of claim 19 wherein the first high priority transaction type is isochronous and the second lower priority request type is asynchronous.

Claim 26

Dependent Claim 117 words

The memory controller of claim 20 further comprising a third in-order request queue that receives memory access requests in order from a first bus to be coupled to the memory controller, the first bus receiving memory access requests from the first and second memory access request queues; a fourth memory access request queue to receive memory access requests from a second bus to be coupled to the memory controller; and a second configurable arbiter coupled to the third and fourth request queues, the second configurable arbiter to prioritize the third in-order request queue over the fourth memory access request queue until a second predetermined maximum number of slices have been serviced from the third in-order request queue.

Claim 27

Dependent Claim 49 words

The memory controller of claim 21 wherein the second configurable arbiter is further to change memory access requests of the second type in the third in-order request queue to the first type When a memory access request of the first type is stored in the third in-order request queue.

Claim 28

Dependent Claim 13 words

The memory controller of claim 19 wherein the first predetermined number is programmable.

Claim 29

Dependent Claim 118 words

A computer system comprising: a processor bus; a dynamic random access memory (DRAM); a memory controller coupled to the processor bus and the DRAM, the memory controller comprising first and second request queues to store memory access requests directed to the DRAM, and a configurable arbiter to dynamically prioritize the first request queue over the second request queue if the first request queue stores a memory access request of a first type, the configurable arbiter further to dynamically prioritize the second request queue over the first request queue before all memory access requests of the first type have been serviced in response to a first predetermined maximum number of memory access requests of the first type being serviced.

Claim 30

Dependent Claim 118 words

A computer system comprising: a processor bus; a dynamic random access memory (DRAM); a memory controller coupled to the processor bus and the DRAM, the memory controller comprising first and second request queues to store memory access requests directed to the DRAM, and a configurable arbiter to dynamically prioritize the first request queue over the second request queue if the first request queue stores a memory access request of a first type, the configurable arbiter further to dynamically prioritize the second request queue over the first request queue before all memory access requests of the first type have been serviced in response to a first predetermined maximum number of memory access requests of the first type being serviced.

Claim 31

Dependent Claim 50 words

The computer system of claim 24 wherein the first type is isochronous, the computer system further comprising: a first peripheral bus coupled to the first request queue to communicate isochronous memory access requests, and a second peripheral bus coupled to the second request queue to communicate asynchronous memory access requests.

Claim 32

Dependent Claim 45 words

The computer system of claim 25 wherein the first request queue is an in-order request queue that receives memory access requests in-order from the processor bus, and the second request queue is a graphics request queue that receives memory access requests from a graphics bus.

Claim 33

Dependent Claim 54 words

The computer system of claim 26 wherein the first request queue is further to change a memory access request of a second type stored in the first request queue to a memory access request of the first type when the memory access request of the first type is stored in the first request queue.

Claim 34

Dependent Claim 33 words

The computer system of claim 27 wherein, if the first request queue does not include a memory access request of the first type, the configurable arbiter operates according to a static timeslicing approach.

Claim 35

Dependent Claim 14 words

The computer system of claim 25 wherein the first predetermined maximum number is programmable.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2006-09-29	2007-03-31	2007-09-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2010-09-29	2011-03-31	2011-09-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2014-09-29	2015-03-31	2015-09-30	$7700.00	Window Closed / Lapsed

Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type

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