Write verify schemes for flash memory with multilevel cells

Claim 2

In a memory device including at least one memory cell having a voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a method for verifying successful programming of the memory cell to a desired state, the method comprising the steps of: selecting a first reference, the first reference corresponding to a first threshold voltage level that defines a first lower bound of a first state; selecting a second reference, the second reference corresponding to a second threshold voltage level that defines a second lower bound of a second state; selecting a third reference, the third reference corresponding to a third threshold voltage level that defines a third lower bound of a third state; applying a programming voltage to the memory cell; sensing the threshold voltage level of the memory cell; comparing the threshold voltage level of the memory cell to the first reference; outputting a first result of comparing the threshold voltage level of the memory cell to the first reference; comparing the threshold voltage level of the memory cell to a selected one of the second reference and the third reference, a selection between the second and third references being made in response to the first result; outputting a second result of comparing the threshold voltage level of the memory cell to the selected one of the second reference and the third reference; comparing the first result and the second result to an expected value, the expected value indicating the desired state; and indicating successful programming if the first result and the second result are equal to the expected value.

Claim 3

The method of claim 1, wherein the step of comparing the threshold voltage level of the memory cell to the one of the second reference and the third reference includes the further steps of: comparing the threshold voltage level of the memory cell to the second reference if the threshold voltage level of the memory cell is less than the first reference as indicated by the first result; and comparing the threshold voltage level of the memory cell to the third reference if the threshold voltage level of the memory cell is greater than the first reference as indicated by the first result.

Claim 4

The method of claim 2, wherein the method further comprises the steps of: repetitively and sequentially performing the steps of applying the programming voltage to the memory cell, comparing the threshold voltage level of the memory cell to the first reference, outputting the first result, comparing the threshold voltage level of the memory cell to the selected one of the second reference and the third reference, outputting the second result, and comparing the first result and the second result to the expected value until the first result and the second result are equal to the expected value if the first result and the second result are not equal to the expected value.

Claim 5

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a method for verifying successful programming of the memory cell to a desired state, the method comprising the steps of: selecting a first reference, the first reference corresponding to a first voltage that defines a lower bound of the predetermined range of threshold voltage levels for the desired state; selecting a second reference, the second reference corresponding to a second voltage that defines an upper bound of the predetermined range of threshold voltage levels for the desired state; applying a programming voltage to the memory cell; sensing the threshold voltage level of the memory cell; comparing the threshold voltage level of the memory cell to the first reference; comparing the threshold voltage level of the memory cell to the second reference; and indicating that the memory cell is programmed to the desired state if the threshold voltage level of the memory cell is greater than the first reference and less than the second reference.

Claim 6

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a method for verifying successful programming of the memory cell to a desired state, the method comprising the steps of: selecting a first reference, the first reference corresponding to a first voltage that defines a lower bound of the predetermined range of threshold voltage levels for the desired state; selecting a second reference, the second reference corresponding to a second voltage that defines an upper bound of the predetermined range of threshold voltage levels for the desired state; applying a programming voltage to the memory cell; sensing the threshold voltage level of the memory cell; comparing the threshold voltage level of the memory cell to the first reference; comparing the threshold voltage level of the memory cell to the second reference; and indicating that the memory cell is programmed to the desired state if the threshold voltage level of the memory cell is greater than the first reference and less than the second reference.

Claim 7

The method of claim 4, wherein the method further comprises the steps of: if the threshold voltage level of the memory cell is less than the threshold voltage level of the first reference, sequentially and repetitively applying a programming voltage to the memory cell and comparing the threshold voltage level of the memory cell to the first and second references until the threshold voltage level of the memory cell is greater than the threshold voltage level of the first reference.

Claim 8

The method of claim 5, wherein the method further includes the step of: indicating that the memory cell is overprogrammed if the threshold voltage level of the memory cell is greater than the second reference.

Claim 9

The method of claim 6, wherein the method further includes the step of: receiving data, the data indicating the desired state of the memory cell, wherein the steps of selecting the first reference and selecting the second reference are performed in response to the data received.

Claim 10

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a method for verifying successful programming of the memory cell to a desired state, the method comprising the steps of: selecting a first reference, the first reference defining a lower bound of the predetermined range of threshold voltage levels for the desired state; applying a programming voltage to the memory cell; sensing the threshold voltage level of the memory cell; comparing the threshold voltage level of the memory cell to the first reference; indicating that the memory cell is programmed to the desired state if the threshold voltage level of the memory cell is greater than the first reference.

Claim 11

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a method for verifying successful programming of the memory cell to a desired state, the method comprising the steps of: selecting a first reference, the first reference defining a lower bound of the predetermined range of threshold voltage levels for the desired state; applying a programming voltage to the memory cell; sensing the threshold voltage level of the memory cell; comparing the threshold voltage level of the memory cell to the first reference; indicating that the memory cell is programmed to the desired state if the threshold voltage level of the memory cell is greater than the first reference.

Claim 12

The method of claim 8, wherein the method further comprises the steps of: sequentially and repetitively applying the programming voltage to the memory cell and comparing the threshold voltage level of the memory cell to the first reference until the threshold voltage level of the memory cell is greater than the threshold voltage level of the first reference if the threshold voltage level of the memory cell is less than the threshold voltage level of the first reference.

Claim 13

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a method for whether the memory cell is overprogrammed, the method comprising the steps of: selecting a first reference, the first reference corresponding to a first voltage that defines an upper bound of the predetermined range of threshold voltage levels for the desired state; sensing the threshold voltage level of the memory cell; comparing the threshold voltage level of the memory cell to the first reference; indicating that the memory cell is overprogrammed if the threshold voltage level of the memory cell is greater than the first reference.

Claim 14

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a method for whether the memory cell is overprogrammed, the method comprising the steps of: selecting a first reference, the first reference corresponding to a first voltage that defines an upper bound of the predetermined range of threshold voltage levels for the desired state; sensing the threshold voltage level of the memory cell; comparing the threshold voltage level of the memory cell to the first reference; indicating that the memory cell is overprogrammed if the threshold voltage level of the memory cell is greater than the first reference.

Claim 15

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a method for refreshing the memory cell to place the memory cell in a desired state, the method comprising the steps of: selecting a first reference, the first reference defining a lower bound of the predetermined range of threshold voltage levels for the desired state; sensing the threshold voltage level of the memory cell; comparing the threshold voltage level of the memory cell to the first reference; sequentially and repetitively applying a programming voltage to the memory cell and comparing the threshold voltage level of the memory cell to the first reference until the threshold voltage level of the memory cell is greater than the threshold voltage level of the first reference if the threshold voltage level of the memory cell is less than the threshold voltage level of the first reference.

Claim 16

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a method for refreshing the memory cell to place the memory cell in a desired state, the method comprising the steps of: selecting a first reference, the first reference defining a lower bound of the predetermined range of threshold voltage levels for the desired state; sensing the threshold voltage level of the memory cell; comparing the threshold voltage level of the memory cell to the first reference; sequentially and repetitively applying a programming voltage to the memory cell and comparing the threshold voltage level of the memory cell to the first reference until the threshold voltage level of the memory cell is greater than the threshold voltage level of the first reference if the threshold voltage level of the memory cell is less than the threshold voltage level of the first reference.

Claim 17

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a write verify circuit for verifying successful programming of the memory cell to a desired state, the write verify circuit comprising: a plurality of read references, each read reference corresponding to a read voltage between states; a first reference, the first reference corresponding to a first voltage that defines a first lower bound of a first state; a second reference, the second reference corresponding to a second voltage that defines a second lower bound of a second state; a third reference, the third reference corresponding to a third voltage that defines a third lower bound of a third state; a control engine coupled to the memory cell and to the first, second and third references for applying a programming voltage to the memory cell to program the memory cell to the desired state, for generating a select signal to select the first, second and third references to sense a present state of the memory cell, for comparing the present state to the desired state, and for indicating successful programming of the memory cell if the present state equals the desired state; a sensing circuit coupled to the memory cell and the control engine, the sensing circuit being coupled to the first, second and third references in response to the select signal, the sensing circuit for sensing the present state of the memory cell, the sensing circuit including: a first comparator coupled to the memory cell, the control engine and the first reference, the first comparator for comparing a cell threshold voltage level corresponding to the memory cell to the first reference, and for outputting a first result to the control engine; a second comparator coupled to the memory cell, the control engine and a selected one of the second reference and the third reference, the second comparator for comparing the cell threshold voltage level to the selected one of the second reference and the third reference, and for outputting a second result to the control engine, wherein the first and second results indicate the present state; and a selector circuit coupled for receiving the first result, the selector circuit for selectively coupling the one of the second reference and the third reference to the second comparator in response to the first result.

Claim 18

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a write verify circuit for verifying successful programming of the memory cell to a desired state, the write verify circuit comprising: a plurality of read references, each read reference corresponding to a read voltage between states; a first reference, the first reference corresponding to a first voltage that defines a first lower bound of a first state; a second reference, the second reference corresponding to a second voltage that defines a second lower bound of a second state; a third reference, the third reference corresponding to a third voltage that defines a third lower bound of a third state; a control engine coupled to the memory cell and to the first, second and third references for applying a programming voltage to the memory cell to program the memory cell to the desired state, for generating a select signal to select the first, second and third references to sense a present state of the memory cell, for comparing the present state to the desired state, and for indicating successful programming of the memory cell if the present state equals the desired state; a sensing circuit coupled to the memory cell and the control engine, the sensing circuit being coupled to the first, second and third references in response to the select signal, the sensing circuit for sensing the present state of the memory cell, the sensing circuit including: a first comparator coupled to the memory cell, the control engine and the first reference, the first comparator for comparing a cell threshold voltage level corresponding to the memory cell to the first reference, and for outputting a first result to the control engine; a second comparator coupled to the memory cell, the control engine and a selected one of the second reference and the third reference, the second comparator for comparing the cell threshold voltage level to the selected one of the second reference and the third reference, and for outputting a second result to the control engine, wherein the first and second results indicate the present state; and a selector circuit coupled for receiving the first result, the selector circuit for selectively coupling the one of the second reference and the third reference to the second comparator in response to the first result.

Claim 19

The write verify circuit of claim 12, wherein the selector circuit couples the second reference to the second comparator if the cell threshold voltage level is greater than the first threshold voltage level.

Claim 20

The write verify circuit of claim 13, wherein the selector circuit couples the third reference to the second comparator if the cell threshold voltage level is less than the first threshold voltage level.

Claim 21

The write verify circuit of claim 14, wherein each of the plurality of read references and the first, second and third references is a reference memory cell.

Claim 22

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a write verify circuit for verifying successful programming of the memory cell to a desired state, the write verify circuit comprising: a plurality of read references, each read reference corresponding to a read voltage between states; a first reference, the first reference corresponding to a first voltage that defines a lower bound of the desired state; a second reference, the second reference corresponding to a second voltage that defines an upper bound of the desired state; a control engine coupled to the memory cell and the first and second references for applying a programming voltage to the memory cell to program the memory cell to the desired state, and for generating a select signal to select the first and second references to sense a present state of the memory cell; a sensing circuit coupled to the memory cell and the control engine, the sensing circuit being coupled to the first and second references in response to the select signal, the sensing circuit for sensing a cell voltage of the memory cell, the sensing circuit including: a first comparator coupled to the memory cell, the control engine and the first reference, the first comparator for comparing the cell threshold voltage level to the first reference, and for asserting a first result signal to the control engine if the cell threshold voltage level is greater than the first reference; a second comparator coupled to the memory cell, the control engine and the second reference, the second comparator for comparing the cell threshold voltage level to the second reference, and for asserting a second result signal to the control engine if the cell threshold voltage level is less than the second reference, wherein assertion of the first and second result signals indicates that the memory cell is successfully programmed.

Claim 23

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a write verify circuit for verifying successful programming of the memory cell to a desired state, the write verify circuit comprising: a plurality of read references, each read reference corresponding to a read voltage between states; a first reference, the first reference corresponding to a first voltage that defines a lower bound of the desired state; a second reference, the second reference corresponding to a second voltage that defines an upper bound of the desired state; a control engine coupled to the memory cell and the first and second references for applying a programming voltage to the memory cell to program the memory cell to the desired state, and for generating a select signal to select the first and second references to sense a present state of the memory cell; a sensing circuit coupled to the memory cell and the control engine, the sensing circuit being coupled to the first and second references in response to the select signal, the sensing circuit for sensing a cell voltage of the memory cell, the sensing circuit including: a first comparator coupled to the memory cell, the control engine and the first reference, the first comparator for comparing the cell threshold voltage level to the first reference, and for asserting a first result signal to the control engine if the cell threshold voltage level is greater than the first reference; a second comparator coupled to the memory cell, the control engine and the second reference, the second comparator for comparing the cell threshold voltage level to the second reference, and for asserting a second result signal to the control engine if the cell threshold voltage level is less than the second reference, wherein assertion of the first and second result signals indicates that the memory cell is successfully programmed.

Claim 24

The write verify circuit of claim 16, wherein each of the first and second references is a reference memory cell.

Claim 25

The write verify circuit of claim 16, wherein the desired state comprises a first value and a second value, the control engine for comparing the first result signal to the first value, and for applying the programming voltage if the first result signal is not equal to the first value.

Claim 26

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a write verify circuit for verifying successful programming of the memory cell to a desired state, the write verify circuit comprising: a plurality of read references, each read reference corresponding to a read voltage between states; a first reference, the first reference corresponding to a first voltage that defines a lower bound of the desired state; a control engine coupled to the memory cell and the first reference for applying a programming voltage to the memory cell to program the memory cell to the desired state, and for generating a select signal to select the first reference to sense a present state of the memory cell; a sensing circuit coupled to the memory cell and the control engine, the sensing circuit being coupled to the first reference in response to the select signal, the sensing circuit for sensing a cell voltage of the memory cell, the sensing circuit including: a first comparator coupled to the memory cell, the control engine and the first reference, the first comparator for comparing the cell threshold voltage level to the first reference, and for outputting a result signal indicating that the memory cell is programmed to the desired state if the cell threshold voltage level is greater than the first reference.

Claim 27

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a write verify circuit for verifying successful programming of the memory cell to a desired state, the write verify circuit comprising: a plurality of read references, each read reference corresponding to a read voltage between states; a first reference, the first reference corresponding to a first voltage that defines a lower bound of the desired state; a control engine coupled to the memory cell and the first reference for applying a programming voltage to the memory cell to program the memory cell to the desired state, and for generating a select signal to select the first reference to sense a present state of the memory cell; a sensing circuit coupled to the memory cell and the control engine, the sensing circuit being coupled to the first reference in response to the select signal, the sensing circuit for sensing a cell voltage of the memory cell, the sensing circuit including: a first comparator coupled to the memory cell, the control engine and the first reference, the first comparator for comparing the cell threshold voltage level to the first reference, and for outputting a result signal indicating that the memory cell is programmed to the desired state if the cell threshold voltage level is greater than the first reference.

Claim 28

The write verify circuit of claim 19, wherein the first reference is a reference memory cell.

Claim 29

The write verify circuit of claim 20, wherein the desired state comprises a first value, the control engine for comparing the first result to the first value, and for applying the programming voltage if the first result is not equal to the first value.

Claim 30

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a circuit for sensing if the memory cell is overprogrammed, the circuit comprising: a plurality of read references, each read reference corresponding to a read voltage between states; a first reference, the first reference corresponding to a first voltage that defines an upper bound of a desired state; a control engine coupled to the memory cell and the first reference for generating a select signal to select the first reference to sense a present state of the memory cell; a sensing circuit coupled to the memory cell and the control engine, the sensing circuit being coupled to the first reference in response to the select signal, the sensing circuit for sensing a cell voltage of the memory cell, the sensing circuit including: a first comparator coupled to the memory cell, the control engine and the first reference, the first comparator for comparing the cell threshold voltage level to the first reference, and for outputting a result signal indicating that the memory cell is overprogrammed if the threshold voltage level of the memory cell is greater than the first reference.

Claim 31

In a memory device including at least one memory cell having a threshold voltage level that indicates one of n possible states, where n is greater than 2, each state corresponding to a predetermined range of threshold voltage levels, a circuit for sensing if the memory cell is overprogrammed, the circuit comprising: a plurality of read references, each read reference corresponding to a read voltage between states; a first reference, the first reference corresponding to a first voltage that defines an upper bound of a desired state; a control engine coupled to the memory cell and the first reference for generating a select signal to select the first reference to sense a present state of the memory cell; a sensing circuit coupled to the memory cell and the control engine, the sensing circuit being coupled to the first reference in response to the select signal, the sensing circuit for sensing a cell voltage of the memory cell, the sensing circuit including: a first comparator coupled to the memory cell, the control engine and the first reference, the first comparator for comparing the cell threshold voltage level to the first reference, and for outputting a result signal indicating that the memory cell is overprogrammed if the threshold voltage level of the memory cell is greater than the first reference.

Claim 32

The write verify circuit of claim 22, wherein the first reference is a reference memory cell.

Claim 33

The write verify circuit of claim 23, wherein the desired state comprises a first value, the control engine for comparing the first result signal to the first value, and for indicating that the memory cell is overprogrammed if the first result signal is not equal to the first value.