US5600592A
Expired / Lapsed
US
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Nonvolatile semiconductor memory device having a word line to which a negative voltage is applied
Assignee: Toshiba Corp
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Filing: 1995-05-08
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Granted: 1997-02-04
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Expires: 2015-05-08
Abstract
Abstract In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval with such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.
Inventors
- 👤 Shigeru Atsumi
- 👤 Sumio Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:39
CPC Classifications
H; H10; H10B; H10B69/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C16/08; H10B41/00; H10B41/40; H10B41/42; H10B41/49
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
114 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate having a P-conductivity type region; stacked gate memory cells each having a control gate, a floating gate, a source, and a drain, said stacked gate memory cells being formed on said P-conductivity type region; a word line connected to the control gates of said memory cells; first means for providing a negative potential to said word line in response to a signal; a first N-channel transistor formed on said substrate, said first N-channel transistor being electrically separated from said P-conductivity type region by a double well structure; and second means for providing a positive potential to said P-conductivity type region in response to said signal.
Claim 2
Dependent Claim
114 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate having a P-conductivity type region; stacked gate memory cells each having a control gate, a floating gate, a source, and a drain, said stacked gate memory cells being formed on said P-conductivity type region; a word line connected to the control gates of said memory cells; first means for providing a negative potential to said word line in response to a signal; a first N-channel transistor formed on said substrate, said first N-channel transistor being electrically separated from said P-conductivity type region by a double well structure; and second means for providing a positive potential to said P-conductivity type region in response to said signal.
Claim 3
Dependent Claim
40 words
A nonvolatile semiconductor memory device according to claim 1, wherein said positive potential is a positive power supply potential which is the same as a potential supplied to the drains of said stacked gate memory cells during a write operation.
Claim 4
Dependent Claim
40 words
A nonvolatile semiconductor memory device according to claim 1, wherein said positive potential is a positive power supply potential which is the same as a potential supplied to the gates of said stacked gate memory cells during a write operation.
Claim 5
Dependent Claim
52 words
A nonvolatile semiconductor memory device according to claim 1, wherein said second means comprises a P-channel transistor connected between a first terminal supplied with said positive potential and said P-conductivity type region, and a second N-channel transistor connected between a second terminal supplied with a reference potential and said P-conductivity type region.
Claim 6
Dependent Claim
40 words
A nonvolatile semiconductor memory device according to claim 4, wherein said positive potential is a positive power supply potential which is the same as a potential supplied to the drains of said stacked gate memory cells during a write operation.
Claim 7
Dependent Claim
40 words
A nonvolatile semiconductor memory device according to claim 4, wherein said positive potential is a positive power supply potential which is the same as a potential supplied to the gates of said stacked gate memory cells during a write operation.
Claim 8
Dependent Claim
16 words
A nonvolatile semiconductor memory device according to claim 4, wherein said reference potential is ground potential.
Claim 9
Dependent Claim
37 words
A nonvolatile semiconductor memory device according to claim 4, wherein a back gate of said P-channel transistor is connected to said first terminal and a back gate of said N-channel transistor is connected to said second terminal.
Claim 10
Dependent Claim
26 words
A nonvolatile semiconductor memory device according to claim 4, wherein said P-channel transistor is formed in an N-conductivity type well formed in said P-conductivity type region.
Claim 11
Dependent Claim
32 words
A nonvolatile semiconductor memory device according to claim 4, wherein said second N-channel transistor is formed on said substrate and electrically separated from said P-conductivity type region by a double well structure.
Claim 12
Dependent Claim
55 words
A nonvolatile semiconductor memory device according to claim 1, further comprising a metal layer formed on a surface area of said semiconductor substrate, which is opposite to a surface area in which said P-conductivity type region, said P-conductivity transistor, said first N-channel transistor, said stacked gate memory cells, and said second N-channel transistor are formed.
Claim 13
Dependent Claim
79 words
A nonvolatile semiconductor memory device according to claim 1, wherein said first means comprises a negative potential generating circuit for generating a negative potential, a switching circuit, and a second N-channel transistor formed on said semiconductor substrate, electrically separated from said semiconductor substrate by a double well structure, said switching circuit and said second N-channel transistor being controlled by said signal to transfer said negative potential to the gates of said stacked gate memory cells through said word line.
Claim 14
Dependent Claim
61 words
A nonvolatile semiconductor memory device according to claim 12, wherein said switching circuit comprises a third N-channel transistor controlled by said signal, connected between said negative potential and a node, and a fourth N-channel transistor controlled by said signal, connected between a reference potential and said node, and said second N-channel transistor is connected between said node and said word line.
Claim 15
Dependent Claim
35 words
A nonvolatile semiconductor memory device according to claim 13, wherein said second, third, and fourth N-channel transistors are formed on said substrate and electrically separated from said P-conductivity type region by a double well structure.
Claim 16
Dependent Claim
79 words
A nonvolatile semiconductor memory device according to claim 1, further comprising third means for providing in response to said signal, to the gates of said stacked gate memory cells through said word line in response to said signal, a first power supply potential from a first terminal during a read operation and a second positive power supply potential from a second terminal during a write operation, said second power supply potential being higher than said first power supply potential.
Claim 17
Dependent Claim
65 words
A nonvolatile semiconductor memory device according to claim 15, wherein said third means comprises a switching circuit and a P-channel transistor connected between the switching circuit and said word line, said switching circuit and said P-channel transistor being controlled by said signal to transfer a selected one of said power supply potentials to the gates of said stacked gate memory cells through said word line.
Claim 18
Dependent Claim
56 words
A nonvolatile semiconductor memory device according to claim 16, wherein said switching circuit of said third means comprises a second N-channel transistor controlled by said signal, connected between said first terminal and a node connected to said P-channel transistor, and a third N-channel transistor controlled by said signal, connected between said second terminal and said node.
Claim 19
Dependent Claim
42 words
A nonvolatile semiconductor memory device according to claim 17, wherein said second and third N-channel transistors constituting said switching circuit of said third means are formed on said substrate and electrically separated from said P-conductivity type region by a double well structure.
Claim 20
Dependent Claim
16 words
A nonvolatile semiconductor memory device according to claim 1, wherein the signal is an erasing signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |