US5828616A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sensing scheme for flash memory with multilevel cells
Assignee: Intel Corp
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Filing: 1997-02-19
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Granted: 1998-10-27
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Expires: 2017-02-19
Abstract
Abstract Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage Vt of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.
Inventors
- 👤 Mark E. Bauer
- 👤 Sanjay Talreja
- 👤 Albert Fazio
- 👤 Gregory Atwood
- 👤 Johnny Javanifard
- 👤 Kevin W. Frary
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:50
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C2211/00; G11C2211/56; G11C2211/563; G11C2211/5632
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
304 words
A flash memory device including at least one flash electrically-erasable programmable read-only memory (EEPROM) cell that stores n bits that indicate one of 2 n states, each state corresponding to a predetermined range of cell charge levels, the flash memory device comprising: a) a first comparator that performs a first comparison of a cell charge level of the flash EEPROM cell and a first reference cell charge level of a first reference cell, wherein a result of the first comparison is output from the first comparator to indicate a value of an n bit of the flash EEPROM cell; b) a selector circuit having an input for receiving the result of the first comparison, the selector circuit selecting one of a second reference cell and a third reference cell in response to the result of the first comparison, the second reference cell being selected if the charge level of the flash EEPROM cell is less than the first reference cell charge level, the third reference cell being selected if the charge level of the flash EEPROM cell is greater than the first reference cell charge level; and c) a second comparator that performs a second comparison of the cell charge level of the flash EEPROM cell and the selected one of a second reference cell charge level of the second reference cell and a third reference cell charge level of the third reference cell, wherein a result of the second comparison is output from the second comparator to indicate an (n-1) bit of the flash EEPROM cell, wherein the first comparator continues to output the result of the first comparison while steps b) and c) are performed such that the first comparator outputs the n bit and the second comparator outputs the (n-1) bit simultaneously to indicate the state of the flash EEPROM cell.
Claim 2
Dependent Claim
304 words
A flash memory device including at least one flash electrically-erasable programmable read-only memory (EEPROM) cell that stores n bits that indicate one of 2 n states, each state corresponding to a predetermined range of cell charge levels, the flash memory device comprising: a) a first comparator that performs a first comparison of a cell charge level of the flash EEPROM cell and a first reference cell charge level of a first reference cell, wherein a result of the first comparison is output from the first comparator to indicate a value of an n bit of the flash EEPROM cell; b) a selector circuit having an input for receiving the result of the first comparison, the selector circuit selecting one of a second reference cell and a third reference cell in response to the result of the first comparison, the second reference cell being selected if the charge level of the flash EEPROM cell is less than the first reference cell charge level, the third reference cell being selected if the charge level of the flash EEPROM cell is greater than the first reference cell charge level; and c) a second comparator that performs a second comparison of the cell charge level of the flash EEPROM cell and the selected one of a second reference cell charge level of the second reference cell and a third reference cell charge level of the third reference cell, wherein a result of the second comparison is output from the second comparator to indicate an (n-1) bit of the flash EEPROM cell, wherein the first comparator continues to output the result of the first comparison while steps b) and c) are performed such that the first comparator outputs the n bit and the second comparator outputs the (n-1) bit simultaneously to indicate the state of the flash EEPROM cell.
Claim 3
Dependent Claim
183 words
A flash memory device comprising: a flash electrically-erasable programmable read-only memory (EEPROM) cell having n bits indicative of 2 n states, each state corresponding to a predetermined range of cell charge levels; a comparator coupled to the flash EEPROM cell; and a decode circuit coupled to the comparator and including n-1 reference cell charge levels, wherein the comparator outputs a first signal in response to a first comparison of a cell charge level of the flash EEPROM cell with a first one of the n-1 reference cell charge levels, wherein the first signal is indicative of an n bit in the flash EEPROM cell, wherein the decode circuit selects one of a second one and a third one of the n-1 reference cell charge levels in response to the first signal, wherein the comparator outputs a second signal in response to a second comparison of the cell charge level of the flash EEPROM cell to the selected one of the second and third reference cell charge levels, and wherein the second signal is indicative of an n-1 bit of the flash EEPROM cell.
Claim 4
Dependent Claim
183 words
A flash memory device comprising: a flash electrically-erasable programmable read-only memory (EEPROM) cell having n bits indicative of 2 n states, each state corresponding to a predetermined range of cell charge levels; a comparator coupled to the flash EEPROM cell; and a decode circuit coupled to the comparator and including n-1 reference cell charge levels, wherein the comparator outputs a first signal in response to a first comparison of a cell charge level of the flash EEPROM cell with a first one of the n-1 reference cell charge levels, wherein the first signal is indicative of an n bit in the flash EEPROM cell, wherein the decode circuit selects one of a second one and a third one of the n-1 reference cell charge levels in response to the first signal, wherein the comparator outputs a second signal in response to a second comparison of the cell charge level of the flash EEPROM cell to the selected one of the second and third reference cell charge levels, and wherein the second signal is indicative of an n-1 bit of the flash EEPROM cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |