EEPROM with split gate source side injection

Claim 2

A memory structure comprising: a source region of a first conductivity type; a drain region of said first conductivity type; a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region; a second channel region of said second conductivity type opposite said first conductivity type, located adjacent said drain region; a transfer channel region of said second conductivity type, located between said first and second channel regions; a first floating gate located above said first channel region; a second floating gate located above said second channel region; a first control gate located above said first floating gate, serving as a steering element associated with said first floating gate; a second control gate located above said second floating gate, serving as a steering element associated with said second floating gate; a third control gate located above said transfer channel region, serving as a control gate of an access transistor, said third control gate also overlying at least a portion of said first and second control gates; a first tunneling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate; and a second tunneling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 3

A memory structure comprising: a source region of a first conductivity type; a drain region of said first conductivity type; a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region, a portion of said first channel region adjacent said source region being doped to said second conductivity type to a dopant concentration greater than that of said first channel region; a second channel region of said second conductivity type opposite said first conductivity type, located adjacent said drain region, a portion of said second channel region adjacent said drain region being doped to said second conductivity type to a dopant concentration greater than that of said second channel region; a transfer channel region of said second conductivity type, located between said first and second channel regions; a first floating gate located above said first channel region; a second floating gate located above said second channel region; a first control gate located above said first floating gate, serving as a steering element associated with said first floating gate; a second control gate located above said second floating gate, serving as a steering element associated with said second floating gate; a third control gate located above said transfer channel region, serving as a control gate of an access transistor; a first tunneling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate; and a second tunneling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 4

A memory structure comprising: a source region of a first conductivity type; a drain region of said first conductivity type; a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region, a portion of said first channel region adjacent said source region being doped to said second conductivity type to a dopant concentration greater than that of said first channel region; a second channel region of said second conductivity type opposite said first conductivity type, located adjacent said drain region, a portion of said second channel region adjacent said drain region being doped to said second conductivity type to a dopant concentration greater than that of said second channel region; a transfer channel region of said second conductivity type, located between said first and second channel regions; a first floating gate located above said first channel region; a second floating gate located above said second channel region; a first control gate located above said first floating gate, serving as a steering element associated with said first floating gate; a second control gate located above said second floating gate, serving as a steering element associated with said second floating gate; a third control gate located above said transfer channel region, serving as a control gate of an access transistor; a first tunneling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate; and a second tunneling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 5

A memory structure comprising: a source region of a first conductivity type; a drain region of said first conductivity type; a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region; a second channel region of said second conductivity type opposite said first conductivity type, located adjacent said drain region; a transfer channel region of said second conductivity type, located between said first and second channel regions; a first floating gate located above said first channel region; a second floating gate located above said second channel region; a first control gate located above said first floating gate, serving as a steering element associated with said first floating gate; a second control gate located above said second floating gate, serving as a steering element associated with said second floating gate; a third control gate located above said transfer channel region, serving as a control gate of an access transistor; a first tunneling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate; a second tunneling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate; a first doped region at the interface of said first channel region and said transfer channel region, said first doped region being doped to said second conductivity type and having a greater dopant concentration than that of said first channel region and said transfer channel region; and a second doped region at the interface of said second channel region and said transfer channel region, said second doped region being doped to said second conductivity type and having a greater dopant concentration than that of said second channel region and said transfer channel region.

Claim 6

A memory structure comprising: a source region of a first conductivity type; a drain region of said first conductivity type; a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region; a second channel region of said second conductivity type opposite said first conductivity type, located adjacent said drain region; a transfer channel region of said second conductivity type, located between said first and second channel regions; a first floating gate located above said first channel region; a second floating gate located above said second channel region; a first control gate located above said first floating gate, serving as a steering element associated with said first floating gate; a second control gate located above said second floating gate, serving as a steering element associated with said second floating gate; a third control gate located above said transfer channel region, serving as a control gate of an access transistor; a first tunneling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate; a second tunneling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate; a first doped region at the interface of said first channel region and said transfer channel region, said first doped region being doped to said second conductivity type and having a greater dopant concentration than that of said first channel region and said transfer channel region; and a second doped region at the interface of said second channel region and said transfer channel region, said second doped region being doped to said second conductivity type and having a greater dopant concentration than that of said second channel region and said transfer channel region.

Claim 7

A memory array having a plurality of memory cells, comprising: a plurality of diffused lines running in a first direction, serving as source and drain regions of said memory cells, each memory cell having a first channel region located adjacent said source region and a second channel region located adjacent said drain region, and a transfer channel region located between its said first and second channel regions; a plurality of first floating gates, each located above said first channel region of an associated one of said memory cells; a plurality of second floating gates, each located above said second channel region of an associated one of said memory cells; a plurality of first control gate lines, running in said first direction, each located above an associated set of said first floating gates and serving as steering elements associated with each said first floating gate; a plurality of second control gate lines, running in said first direction, each located above an associated set of said second floating gates and serving as steering elements associated with each said second floating gate; and a plurality of row lines, running in a second direction generally perpendicular to said first direction, forming a set of third control gates above said transfer channel regions of each memory cell, overlying at least a portion of associated ones of said first and second control gates and serving as control gates of access transistors of associated memory cells, wherein each of said memory cells is associated with the intersection of one of said diffused lines and one of said row lines, and wherein each memory cell includes a first tunnelling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate, and wherein each memory cell includes a second tunnelling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 8

A memory array having a plurality of memory cells, comprising: a plurality of diffused lines running in a first direction, serving as source and drain regions of said memory cells, each memory cell having a first channel region located adjacent said source region and a second channel region located adjacent said drain region, and a transfer channel region located between its said first and second channel regions; a plurality of first floating gates, each located above said first channel region of an associated one of said memory cells; a plurality of second floating gates, each located above said second channel region of an associated one of said memory cells; a plurality of first control gate lines, running in said first direction, each located above an associated set of said first floating gates and serving as steering elements associated with each said first floating gate; a plurality of second control gate lines, running in said first direction, each located above an associated set of said second floating gates and serving as steering elements associated with each said second floating gate; and a plurality of row lines, running in a second direction generally perpendicular to said first direction, forming a set of third control gates above said transfer channel regions of each memory cell, overlying at least a portion of associated ones of said first and second control gates and serving as control gates of access transistors of associated memory cells, wherein each of said memory cells is associated with the intersection of one of said diffused lines and one of said row lines, and wherein each memory cell includes a first tunnelling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate, and wherein each memory cell includes a second tunnelling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 9

A memory array having a plurality of memory cells, comprising: a plurality of diffused lines running in a first direction, serving as source and drain regions of said memory cells, each memory cell having a first channel region located adjacent said source region, a portion of said first channel region adjacent said source region being doped to said second conductivity type to a dopant concentration greater than that of said first channel region and a second channel region located adjacent said drain region, a portion of said second channel region adjacent said drain region being doped to said second conductivity type to a dopant concentration greater than that of said second channel region, and a transfer channel region located between its said first and second channel regions; a plurality of first floating gates, each located above said first channel region of an associated one of said memory cells; a plurality of second floating gates, each located above said second channel region of an associated one of said memory cells; a plurality of first control gate lines, running in said first direction, each located above an associated set of said first floating gates and serving as steering elements associated with each said first floating gate; a plurality of second control gate lines, running in said first direction, each located above an associated set of said second floating gates and serving as steering elements associated with each said second floating gate; and a plurality of row lines, running in a second direction generally perpendicular to said first direction, forming a set of third control gates above said transfer channel regions of each memory cell, and serving as control gates of access transistors of associated memory cells, wherein each of said memory cells is associated with the intersection of one of said diffused lines and one of said row lines, and wherein each memory cell includes a first tunnelling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate, and wherein each memory cell includes a second tunnelling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 10

A memory array having a plurality of memory cells, comprising: a plurality of diffused lines running in a first direction, serving as source and drain regions of said memory cells, each memory cell having a first channel region located adjacent said source region, a portion of said first channel region adjacent said source region being doped to said second conductivity type to a dopant concentration greater than that of said first channel region and a second channel region located adjacent said drain region, a portion of said second channel region adjacent said drain region being doped to said second conductivity type to a dopant concentration greater than that of said second channel region, and a transfer channel region located between its said first and second channel regions; a plurality of first floating gates, each located above said first channel region of an associated one of said memory cells; a plurality of second floating gates, each located above said second channel region of an associated one of said memory cells; a plurality of first control gate lines, running in said first direction, each located above an associated set of said first floating gates and serving as steering elements associated with each said first floating gate; a plurality of second control gate lines, running in said first direction, each located above an associated set of said second floating gates and serving as steering elements associated with each said second floating gate; and a plurality of row lines, running in a second direction generally perpendicular to said first direction, forming a set of third control gates above said transfer channel regions of each memory cell, and serving as control gates of access transistors of associated memory cells, wherein each of said memory cells is associated with the intersection of one of said diffused lines and one of said row lines, and wherein each memory cell includes a first tunnelling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate, and wherein each memory cell includes a second tunnelling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 11

A memory array having a plurality of memory cells, comprising: a plurality of diffused lines running in a first direction, serving as source and drain regions of said memory cells, each memory cell having a first channel region located adjacent said source region and a second channel region located adjacent said drain region, and a transfer channel region located between its said first and second channel regions; a first doped region at the interface of each said first channel region and said transfer channel region, said first doped region being doped to said second conductivity type and having a greater dopant concentration than that of said first channel region and said transfer channel region; a second doped region at the interface of each said second channel region and said transfer channel region, said second doped region being doped to said second conductivity type and having a greater dopant concentration than that of said second channel region and said transfer channel region a plurality of first floating gates, each located above said first channel region of an associated one of said memory cells; a plurality of second floating gates, each located above said second channel region of an associated one of said memory cells; a plurality of first control gate lines, running in said first direction, each located above an associated set of said first floating gates and serving as steering elements associated with each said first floating gate; a plurality of second control gate lines, running in said first direction, each located above an associated set of said second floating gates and serving as steering elements associated with each said second floating gate; and a plurality of row lines, running in a second direction generally perpendicular to said first direction, forming a set of third control gates above said transfer channel regions of each memory cell, and serving as control gates of access transistors of associated memory cells, wherein each of said memory cells is associated with the intersection of one of said diffused lines and one of said row lines, and wherein each memory cell includes a first tunnelling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate, and wherein each memory cell includes a second tunnelling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 12

A memory array having a plurality of memory cells, comprising: a plurality of diffused lines running in a first direction, serving as source and drain regions of said memory cells, each memory cell having a first channel region located adjacent said source region and a second channel region located adjacent said drain region, and a transfer channel region located between its said first and second channel regions; a first doped region at the interface of each said first channel region and said transfer channel region, said first doped region being doped to said second conductivity type and having a greater dopant concentration than that of said first channel region and said transfer channel region; a second doped region at the interface of each said second channel region and said transfer channel region, said second doped region being doped to said second conductivity type and having a greater dopant concentration than that of said second channel region and said transfer channel region a plurality of first floating gates, each located above said first channel region of an associated one of said memory cells; a plurality of second floating gates, each located above said second channel region of an associated one of said memory cells; a plurality of first control gate lines, running in said first direction, each located above an associated set of said first floating gates and serving as steering elements associated with each said first floating gate; a plurality of second control gate lines, running in said first direction, each located above an associated set of said second floating gates and serving as steering elements associated with each said second floating gate; and a plurality of row lines, running in a second direction generally perpendicular to said first direction, forming a set of third control gates above said transfer channel regions of each memory cell, and serving as control gates of access transistors of associated memory cells, wherein each of said memory cells is associated with the intersection of one of said diffused lines and one of said row lines, and wherein each memory cell includes a first tunnelling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate, and wherein each memory cell includes a second tunnelling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 13

The memory structure as in claims 1, 2, 3, 4, 5, or 6 wherein said first conductivity type is N and said second conductivity type is P.

Claim 14

The memory structure as in claim 7 wherein said second conductivity type is provided by boron dopants.

Claim 15

The memory structure as in claims 1, 2, 3, 4, 5, or 6 wherein said floating gates comprise a first layer of polycrystalline silicon, said first control gates comprise a second layer of polycrystalline silicon, and said third control gate comprises a third layer of polycrystalline silicon.

Claim 16

The memory structure as in claims 1, 2, 3, 4, 5, or 6 which is capable of storing one of two logical states.

Claim 17

The memory array as in claim 10 wherein said floating gates establish one of a plurality of predetermined charge levels for storing one of two logical states.

Claim 18

The memory array as in claim 10 wherein said floating gates establish one of a plurality of predetermined charge levels for storing one of more than two logical states.

Claim 19

The memory structure as in claims 1, 2, 3, 4, 5, or 6 wherein said source region and said drain region comprise buried diffusions.

Claim 20

The memory structure as in claim 12 which further comprises a relatively thick dielectric layer overlying said buried diffusions.

Claim 21

The memory structure as in claims 1, 2, 3, 4, 5, or 6 wherein said transfer channel is doped to said second conductivity type to a doped concentration greater than that of said first and second channel regions.

Claim 22

The memory structure as in claims 1, 2, 3, 4, 5, or 6 wherein said transfer channel is counter doped to said second conductivity type to a net doped concentration less than that of said first and second channel regions.

Claim 23

The memory array as in claims 4, 5, or 6 organized into a plurality of sectors, each sector comprising one or more rows and organized such that erasure of all cells of a sector is performed simultaneously.

Claim 24

The memory array as in claims 4, 5, or 6 organized as a virtual ground array.

Claim 25

The memory array as in claims 4, 5, or 6 wherein said one of first or second floating gates in alternate cells in a given row are verified simultaneously.

Claim 26

The memory array as in claim 19 wherein an entire row is verified utilizing four verification operations.

Claim 27

The memory array as in claims 4, 5, or 6 wherein said one of first or second floating gates of alternate cells in a given row are programmed simultaneously by placing data associated with each memory cell to be programmed on its associated diffused lines.

Claim 28

The memory array as in claim 21 wherein an entire row is programmed utilizing four program operations.

Claim 29

A memory array comprising a plurality of sectors, each sector comprising: a plurality of adjacent bit lines running in a first direction to form a corresponding plurality of columns; a plurality of steering lines running in said first direction; a plurality of word lines and their corresponding erase lines running in a second direction generally perpendicular to said first direction to form a corresponding plurality of rows; and a plurality of memory cells, each memory cell being associated with the intersection of one of said bit lines and one of said word lines, and each of said plurality of memory cells capable of being simultaneously erased.

Claim 30

A memory array comprising a plurality of sectors, each sector comprising: a plurality of adjacent bit lines running in a first direction to form a corresponding plurality of columns; a plurality of steering lines running in said first direction; a plurality of word lines and their corresponding erase lines running in a second direction generally perpendicular to said first direction to form a corresponding plurality of rows; and a plurality of memory cells, each memory cell being associated with the intersection of one of said bit lines and one of said word lines, and each of said plurality of memory cells capable of being simultaneously erased.

Claim 31

The structure as in claim 23 wherein said word lines serve as said erase lines.

Claim 32

The structure as in claim 23 in which said memory cell is capable of storing one of two logical states.

Claim 33

The memory array as in claim 23 organized as a virtual ground array.

Claim 34

The memory array as in claim 23 which further comprises: a plurality of diffused lines running in said first direction, serving as said bit lines and forming source and drain regions of said memory cells, each memory cell having a first channel region located adjacent said source region and a second channel region located adjacent said drain region, and a transfer channel region located between its said first and second channel regions; a plurality of first floating gates, each located above said first channel region of an associated one of said memory cells; a plurality of second floating gates, each located above said second channel region of an associated one of said memory cells; a plurality of first control gate lines, running in said first direction, each located above an associated set of said first floating gates and serving as those of said steering lines associated with each said first floating gate; a plurality of second control gate lines, running in said first direction, each located above an associated set of said second floating gates and serving as those of said steering lines associated with each said second floating gate; and a plurality of row lines serving as said word lines, running in said second direction generally perpendicular to said first direction, forming a set of third control gates above said transfer channel regions of each memory cell, overlying at least a portion of associated ones of said first and second control gates and serving as control gates of access transistors of associated memory cells, wherein each of said memory cells is associated with the intersection of one of said diffused lines and one of said row lines, and wherein each memory cell includes a first tunnelling zone formed between said first floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said first floating gate, and wherein each memory cell includes a second tunnelling zone formed between said second floating gate and said third control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said second floating gate.

Claim 35

The memory array as in claim 27 wherein said one of first or second floating gates in alternate cells in a given row are verified simultaneously.

Claim 36

The memory array as in claim 28 wherein an entire row is verified utilizing four verification operations.

Claim 37

The memory array as in claim 27 wherein alternate cells in a given row are programmed simultaneously by placing data associated with each memory cell to be programmed on its associated bit line.

Claim 38

The memory array as in claim 30 wherein an entire row is programmed utilizing four program operations.

Claim 39

The structure as in claims 1, 2, 3, 4, 5, 6, or 23 which further comprises steering bias circuitry capable of providing steering bias voltage levels less than zero.

Claim 40

The structure as in claim 23 in which said memory cell is capable of storing one of more than two logical states.

Claim 41

The memory structure as in claims 1, 2, 3, 4, 5, or 6 which is capable of storing one of more than two logical states.