Semiconductor device power supply wiring structure

Claim 2

A semiconductor device, comprising: a semiconductor integrated circuit provided on a main surface of a semiconductor substrate; a plurality of bonding pads provided for connection with said semiconductor integrated circuit, arranged along opposing longitudinal sides of said semiconductor integrated circuit on a main surface of said semiconductor substrate; an interconnection layer provided on said semiconductor integrated circuit with an insulating member interposed; a first plurality of lead frames connected to said interconnection layer by a first plurality of wires; and a second plurality of lead frames connected to prescribed bonding pads by a second plurality of wires, said prescribed bonding pads being connected to said interconnection layer by a third plurality of wires.

Claim 3

The semiconductor device according to claim 1, wherein said interconnection layer has a power supply interconnection layer and a ground interconnection layer.

Claim 4

The semiconductor device according to claim 2, wherein said third plurality of wires include a wire connecting said power supply interconnection layer to said bonding pad without crossing said ground interconnection layer, and a wire connecting said ground interconnection layer to said bonding pad without crossing said power supply interconnection layer.

Claim 5

The semiconductor device according to claim 2, wherein said power supply interconnection layer has a first power supply interconnection layer extending in a longitudinal direction of said semiconductor substrate, and a plurality of second power supply interconnection layers branching from the first power supply interconnection layer, and said ground interconnection layer has a first ground interconnection layer extending in the longitudinal direction of said semiconductor substrate and a plurality of second ground interconnection layers branching from the first ground interconnection layer.

Claim 6

A semiconductor device, comprising: a semiconductor integrated circuit provided on a main surface of a semiconductor substrate; a plurality of bonding pads provided for connection with said semiconductor integrated circuit, arranged along opposing longitudinal sides of said semiconductor integrated circuit on the main surface of said semiconductor substrate; a first conductive layer provided on a rear surface of said semiconductor substrate with a first insulating film interposed; a plurality of contact electrodes provided on a surface of said first insulating film which faces the semiconductor substrate, each contact electrode connected to a prescribed one of said bonding pads by a wiring; a second conductive layer formed on said first conductive layer with a second insulating film interposed; and a plurality of bump electrodes formed on said second conductive layer with a third insulating film interposed, for connection with external terminals; said semiconductor device further comprising a first interconnection for connecting a prescribed one of said bump electrodes to said first conductive layer through said second insulating film, said second conductive layer and said third insulating film; a second interconnection for connecting a prescribed one of said bump electrodes and said second conductive layer through said third insulating film; a third interconnection for connecting a prescribed one of said contact electrodes and said first conductive layer through said first insulating film; a fourth interconnection for connecting a prescribed one of said contact electrodes to said second conductive layer through said first insulating film, said first conductive layer and said second insulating film; and a fifth interconnection for connecting a prescribed one of said contact electrodes and a prescribed one of said bump electrodes through said first insulating film, said first conductive layer, said second insulating film, said second conductive layer and said third insulating film.

Claim 7

A semiconductor device, comprising: a semiconductor integrated circuit provided on a main surface of a semiconductor substrate; a plurality of bonding pads provided for connection with said semiconductor integrated circuit, arranged along opposing longitudinal sides of said semiconductor integrated circuit on the main surface of said semiconductor substrate; a first conductive layer provided on a rear surface of said semiconductor substrate with a first insulating film interposed; a plurality of contact electrodes provided on a surface of said first insulating film which faces the semiconductor substrate, each contact electrode connected to a prescribed one of said bonding pads by a wiring; a second conductive layer formed on said first conductive layer with a second insulating film interposed; and a plurality of bump electrodes formed on said second conductive layer with a third insulating film interposed, for connection with external terminals; said semiconductor device further comprising a first interconnection for connecting a prescribed one of said bump electrodes to said first conductive layer through said second insulating film, said second conductive layer and said third insulating film; a second interconnection for connecting a prescribed one of said bump electrodes and said second conductive layer through said third insulating film; a third interconnection for connecting a prescribed one of said contact electrodes and said first conductive layer through said first insulating film; a fourth interconnection for connecting a prescribed one of said contact electrodes to said second conductive layer through said first insulating film, said first conductive layer and said second insulating film; and a fifth interconnection for connecting a prescribed one of said contact electrodes and a prescribed one of said bump electrodes through said first insulating film, said first conductive layer, said second insulating film, said second conductive layer and said third insulating film.

Claim 8

The semiconductor device according to claim 5, wherein said first conductive layer is a power supply potential layer and said second conductive layer is a ground potential layer.

Claim 9

The semiconductor device according to claim 4, wherein said plurality of second ground interconnection layers branch in a vertical direction from the first ground interconnection layer.

Claim 10

The semiconductor device according to claim 4, wherein said first power supply interconnection layer is arranged on one side of said semiconductor substrate, and said second power supply interconnection layer is arranged to the other side of said semiconductor substrate from said first power supply interconnection layer.

Claim 11

The semiconductor device according to claim 4, wherein said first power supply interconnection layer is connected to said bonding pad arranged on one side of said semiconductor substrate using one of said third plurality of wires, and said second power supply interconnection layer is connected to said bonding pad arranged on the other side of said semiconductor substrate from said first power supply interconnection layer using said third plurality of wires.

Claim 12

The semiconductor device according to claim 1, wherein said interconnection layer has a power supply interconnection segment and a ground interconnection segment.

Claim 13

The semiconductor device according to claim 10, wherein said third plurality of wires include a wire connecting said power supply interconnection segment to said bonding pad without crossing said ground interconnection segment, and a wire connecting said ground interconnection segment to said bonding pad without crossing said power supply interconnection segment.

Claim 14

The semiconductor device according to claim 1, wherein said bonding pad, said interconnection layer and said lead frame are arranged in accordance with a pin layout of a standardized TSOP type semiconductor package.

Claim 15

A semiconductor device comprising: a semiconductor integrated circuit provided on a main surface of a semiconductor substrate; an interconnection layer provided on said semiconductor integrated circuit with an insulator interposed; a bonding pad disposed on one side of said semiconductor integrated circuit and on the main surface of the semiconductor substrate, and connected to said interconnection layer with a first wire; a first lead frame connected to said interconnection layer with a second wire; and a second lead frame connected to said bonding pad with a third wire.

Claim 16

A semiconductor device comprising: a semiconductor integrated circuit provided on a main surface of a semiconductor substrate; an interconnection layer provided on said semiconductor integrated circuit with an insulator interposed; a bonding pad disposed on one side of said semiconductor integrated circuit and on the main surface of the semiconductor substrate, and connected to said interconnection layer with a first wire; a first lead frame connected to said interconnection layer with a second wire; and a second lead frame connected to said bonding pad with a third wire.

Claim 17

The semiconductor device according to claim 13, wherein said interconnection layer includes an interconnection segment, and said bonding pad and said first lead frame are connected to the interconnection segment with the first and second wire respectively.

Claim 18

The semiconductor device according to claim 14, wherein the interconnection segment includes a first section disposed along said one side of said semiconductor integrated circuit, and a second section extending from the first section toward another side opposing to said one side of said semiconductor integrated circuit.

Claim 19

The semiconductor device according to claim 14, wherein the interconnection segment includes a first section extending to a first direction along said one side of said semiconductor integrated circuit, and a second section along a second direction crossing to the first direction; and said semiconductor device further comprises another bonding pad disposed on another side opposing to said one side of said semiconductor integrated circuit, and connected to the interconnection segment with a fourth wire.

Claim 20

The semiconductor device according to claim 13, wherein said interconnection layer includes a first interconnection segment and a second interconnection segment separated from the first interconnection segment, said bonding pad is connected to the first interconnection segment with the first wire, and said first lead frame is connected to the second interconnection segment with the second wire.

Claim 21

The semiconductor device according to claim 17, wherein the first interconnection segment includes a first section extending along said one side of said semiconductor integrated circuit, and a second section extending toward another side opposing to said one side of said semiconductor integrated circuit.

Claim 22

The semiconductor device according to claim 18, further comprising another bonding pad disposed on said other side of said semiconductor integrated circuit, and connected to the first interconnection segment with a fourth wire.

Claim 23

The semiconductor device according to claim 17, wherein the second interconnection segment includes a first section extending along said one side of said semiconductor integrated circuit, and a second section extending toward another side opposing to said one side of said semiconductor integrated circuit.

Claim 24

The semiconductor device according to claim 20, further comprising another bonding pad disposed on said other side of said semiconductor integrated circuit, and connected to the second interconnection segment with a fourth wire.

Claim 25

The semiconductor device according to claim 13, each of said first and second lead frames supplies a power supply potential, said first and second lead frames are arranged facing said one side of said semiconductor integrated circuit, and said semiconductor device further comprises; another bonding pad disposed on another side of said semiconductor integrated circuit and on the main surface of the semiconductor substrate, and connected to said interconnection layer with a fourth wire; and third and fourth lead frames arranged facing said other side of said semiconductor integrated circuit and each supplying a ground potential, the third lead frame being connected to said interconnection layer with a fifth wire, the fourth lead frame being connected to said other bonding pad with a sixth wire.

Claim 26

The semiconductor device according to claim 13, further comprising a third lead frame, and wherein each of said first, second and third lead frames supplies a power supply potential, said first, second and third lead frames are arranged facing said one side of said semiconductor integrated circuit, said second lead frame is arranged near one of two sides different from said one side and said another a side opposing to said one side of said semiconductor integrated circuit, said third lead frame is arranged near another of said two sides of said semiconductor integrated circuit, and said first lead frame is arranged between said second and third lead frames.

Claim 27

The semiconductor device according to claim 13, further comprising a third lead frame, and wherein each of said first, second and third lead frames supplies a ground potential, said first, second and third lead frames are arranged facing said one side of said semiconductor integrated circuit, said second lead frame is arranged near one of two sides different from said one side and said another side opposing to said one side of said semiconductor integrated circuit, said third lead frame is arranged near another of said two sides of said semiconductor integrated circuit, and said first lead frame is arranged between said second and third lead frames.