Memory cell with antifuse layer formed at diode junction

Claim 2

A three-dimensional memory having a plurality of memory cells disposed at several layers above a substrate, each cell comprising: a first polysilicon region of a first conductivity type, doped to a level of at least 1×10 20 atoms cm −3 ; a second polysilicon region of a second conductivity type doped to a level of approximately 1×10 17 atoms cm −3 ; and an antifuse region disposed between the first and second regions such that when the antifuse region is breached, a diode is formed at the junction of the first and second regions.

Claim 3

The memory defined by claim 1 , wherein the antifuse region of the memory cell is between 20-50 Å thick and formed from silicon dioxide.

Claim 4

The memory defined by claim 1 , wherein the first region of each memory cell is doped to a level of approximately 1×10 21 atoms cm −3 or greater.

Claim 5

The memory defined by claim 1 or 2 , wherein the first conductivity type of the memory cells is P type, and the second conductivity type of the memory cells is N type.

Claim 6

In a three-dimensional memory having a plurality of memory cells on a plurality of levels where each memory cell includes a silicon dioxide region disposed between a first polysilicon region and a second polysilicon region of opposite conductivity type to the first polysilicon region, and where the silicon dioxide layer is breached when the cell is programmed for one binary state, an improvement in memory cell wherein the first polysilicon region is doped to a level in excess of 1×10 20 atoms cm −3 and the second polysilicon region is doped to a level or approximately 1×10 17 atoms cm −3 .

Claim 7

In a three-dimensional memory having a plurality of memory cells on a plurality of levels where each memory cell includes a silicon dioxide region disposed between a first polysilicon region and a second polysilicon region of opposite conductivity type to the first polysilicon region, and where the silicon dioxide layer is breached when the cell is programmed for one binary state, an improvement in memory cell wherein the first polysilicon region is doped to a level in excess of 1×10 20 atoms cm −3 and the second polysilicon region is doped to a level or approximately 1×10 17 atoms cm −3 .

Claim 8

The improvement of claim 5 , wherein the first polysilicon region is a P type region.

Claim 9

The improvement of claim 6 , wherein the doping level of the first polysilicon region is approximately 1×10 21 atoms cm −3 or greater.

Claim 10

The improvement of claims 5 or 7 , wherein the silicon dioxide region is approximately 20-50 Å thick.