US6754102B2
Expired / Lapsed
US
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Method for programming a three-dimensional memory array incorporating serial chain diode stack
Assignee: SanDisk Technologies LLC
•
Filing: 2002-09-24
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Granted: 2004-06-22
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Expires: 2022-09-24
Abstract
Abstract A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N 2 memory cells, rather than approximately 3N 2 memory cells as with prior arrays.
Inventors
- 👤 Bendik Kleveland
- 👤 Roy E. Scheuerlein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 03:47
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/025; B; B82; B82Y; B82Y10/00; G11C13/00; G11C13/0002; G11C13/0009; G11C13/0014; G11C13/0021; G11C13/0023; G11C13/0028; G11C17/00; G11C17/14; G11C17/16; G11C17/165; G11C17/18; G11C7/00; G11C7/06; G11C7/062; G11C7/067; G11C7/18; G11C8/00; G11C8/08; G11C8/10; H; H10; H10B; H10B20/00; H10B20/20; H10B20/25; H10D; H10D88/00; G11C13/0004; G11C2207/00; G11C2207/06; G11C2207/063; G11C2213/00; G11C2213/70; G11C2213/71; G11C2213/72
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
139 words
In a multi-level memory array comprising a plurality of conductors on each level of the memory array, forming a memory cell at each intersection between conductors of adjacent levels, each cell having a respective directionality in common with cells of at least one adjacent level, a method for programming a selected memory cell within a selected memory plane, said method comprising the steps of: forward biasing the selected memory cell with a programming voltage; reverse biasing memory cells within the selected memory plane that do not share a conductor with the selected memory cell; and forward biasing unselected memory cells on at least memory planes adjacent to the selected memory plane, but only those cells that do not share a conductor with the selected memory cell, to a voltage between zero and a turn-on voltage for the memory cell.
Claim 2
Dependent Claim
139 words
In a multi-level memory array comprising a plurality of conductors on each level of the memory array, forming a memory cell at each intersection between conductors of adjacent levels, each cell having a respective directionality in common with cells of at least one adjacent level, a method for programming a selected memory cell within a selected memory plane, said method comprising the steps of: forward biasing the selected memory cell with a programming voltage; reverse biasing memory cells within the selected memory plane that do not share a conductor with the selected memory cell; and forward biasing unselected memory cells on at least memory planes adjacent to the selected memory plane, but only those cells that do not share a conductor with the selected memory cell, to a voltage between zero and a turn-on voltage for the memory cell.
Claim 3
Dependent Claim
26 words
The invention defined in claim 1 further comprising: reverse biasing memory cells within an adjacent memory plane that share a conductor with the selected memory cell.
Claim 4
Dependent Claim
51 words
The invention defined in claim 1 further comprising: forward biasing unselected memory cells on at least memory planes adjacent to the selected memory plane, but only those cells that do not share a conductor with the selected memory cell, to a voltage in a range of about 0.2 to 1.0 volts.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-06-22 | 2007-12-22 | 2008-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-06-22 | 2011-12-22 | 2012-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-06-22 | 2015-12-22 | 2016-06-22 | $7700.00 | Window Closed / Lapsed |