US7177183B2
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Multiple twin cell non-volatile memory array and logic block structure and method therefor
Assignee: SanDisk Technologies LLC
•
Filing: 2003-09-30
•
Granted: 2007-02-13
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Expires: 2023-09-30
Abstract
Abstract Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.
Inventors
- 👤 Roy E. Scheuerlein
- 👤 Luca Fasoli
- 👤 Mark G. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:27
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G11C15/046; G11C8/00; G11C8/10; G11C8/14; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 58
Claim 1
Independent Claim
65 words
A non-volatile memory cell array comprising within a first array block a first plurality of X-lines configured to be individually selected in a write mode of operation and configured to be simultaneously selected in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line and also associated with a second Y-line group numbering at least one Y-line.
Claim 2
Dependent Claim
65 words
A non-volatile memory cell array comprising within a first array block a first plurality of X-lines configured to be individually selected in a write mode of operation and configured to be simultaneously selected in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line and also associated with a second Y-line group numbering at least one Y-line.
Claim 3
Dependent Claim
39 words
The memory array as recited in claim 1 wherein the first and second Y-line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit.
Claim 4
Dependent Claim
20 words
The memory may as recited in claim 2 wherein the first and second Y-line groups each numbers only one Y-line.
Claim 5
Dependent Claim
21 words
The memory may as recited in claim 2 wherein the first and second Y-line groups each numbers more than one Y-line.
Claim 6
Dependent Claim
39 words
The memory array as recited in claim 2 further comprising a reference signal operably coupled to either the true or complement input of the sense amplifier, wherein the first and second Y-line groups each numbers more than one Y-line.
Claim 7
Dependent Claim
16 words
The memory array as recited in claim 5 wherein the reference signal comprises a reference current.
Claim 8
Dependent Claim
37 words
The memory array as recited in claim 1 wherein: the first Y-line group includes more than one Y-line; and each of the first Y-line group is configured to be simultaneously selected in a read mode of operation.
Claim 9
Dependent Claim
17 words
The memory array as recited in claim 1 wherein the memory array comprises passive element memory cells.
Claim 10
Dependent Claim
16 words
The memory array as recited in claim 8 wherein the memory array comprises anti-fuse memory cells.
Claim 11
Dependent Claim
16 words
The memory array as recited in claim 8 wherein the memory array comprises magnetoresistive memory cells.
Claim 12
Dependent Claim
16 words
The memory array as recited in claim 1 wherein the memory array comprises EEPROM memory cells.
Claim 13
Dependent Claim
23 words
The memory array as recited in claim 1 wherein the memory array comprises a two-dimensional memory array having one plane of memory cells.
Claim 14
Dependent Claim
25 words
The memory array as recited in claim 1 wherein the memory array comprises a three-dimensional memory array having more than one plane of memory cells.
Claim 15
Dependent Claim
26 words
The memory array as recited in claim 13 wherein the first plurality of X-lines comprises X-lines disposed on more than one layer of the memory array.
Claim 16
Dependent Claim
26 words
The memory array as recited in claim 13 wherein the first plurality of X-lines comprises X-lines disposed only on a single layer of the memory array.
Claim 17
Dependent Claim
21 words
The memory array as recited in claim 1 configured to perform threshold logic upon one or more inputs to the array.
Claim 18
Dependent Claim
34 words
The memory array as recited in claim 1 further comprising a second plurality of X-lines configured to be simultaneously selected in a read mode of operation and each associated with the first Y-line group.
Claim 19
Dependent Claim
50 words
The memory array as recited in claim 17 further comprising a third plurality of X-lines associated with the first Y-line group, said third plurality of X-lines being configured, in a read mode of operation, to be simultaneously selected at certain times when the first plurality of X-lines is not selected.
Claim 20
Dependent Claim
67 words
The memory array as recited in claim 18 further comprising: a fourth plurality of X-lines associated with the first Y-line group, said fourth plurality of X-lines being configured, in a read mode of operation, to be simultaneously selected when the second plurality of X-lines is not selected; wherein each Y-line of the second Y-line group is associated with the first, second, third, and fourth pluralities of X-lines.
Claim 21
Dependent Claim
21 words
The memory array as recited in claim 17 configured to perform threshold logic upon one or more inputs to the array.
Claim 22
Dependent Claim
23 words
The memory array as recited in claim 17 configured to perform weighted input threshold logic upon one or more inputs to the array.
Claim 23
Dependent Claim
13 words
The memory array as recited in claim 1 wherein X-lines comprise word lines.
Claim 24
Dependent Claim
15 words
The memory may as recited in claim 1 configured as a content addressable memory array.
Claim 25
Dependent Claim
46 words
The memory array as recited in claim 1 wherein: each of the first Y-line group is configured to be simultaneously selected in a read mode of operation; and each of the second Y-line group is configured to be simultaneously selected in a read mode of operation.
Claim 26
Dependent Claim
26 words
The memory array as recited in claim 1 embodied in computer readable descriptive form suitable for use in design, test or fabrication of an integrated circuit.
Claim 27
Independent Claim
146 words
A method of operating a non-volatile memory array comprising: programming individual memory cells associated with a first X-line group of at least one X-line within a first array block and further associated with a first Y-line group of at least one Y-line within the first array block until a desired first aggregate memory cell read current is obtained when simultaneously selecting all the first group of X-lines and all the first group of Y-lines, at least one of the first X-line group and first Y-line group including more than one such X-line or Y-line, and each of the first X-line aroup associated with a second Y-line group numbering at least one Y-line; and reading the memory array by simultaneously selecting all the first group of X-lines and all the first group of Y-lines and generating a signal responsive to the first aggregate memory cell read current.
Claim 28
Independent Claim
146 words
A method of operating a non-volatile memory array comprising: programming individual memory cells associated with a first X-line group of at least one X-line within a first array block and further associated with a first Y-line group of at least one Y-line within the first array block until a desired first aggregate memory cell read current is obtained when simultaneously selecting all the first group of X-lines and all the first group of Y-lines, at least one of the first X-line group and first Y-line group including more than one such X-line or Y-line, and each of the first X-line aroup associated with a second Y-line group numbering at least one Y-line; and reading the memory array by simultaneously selecting all the first group of X-lines and all the first group of Y-lines and generating a signal responsive to the first aggregate memory cell read current.
Claim 29
Dependent Claim
113 words
The method of claim 26 further comprising: programming individual memory cells associated with the first X-line group and further associated with the second Y-line group of at least one Y-line until a desired second aggregate memory cell read current is obtained when simultaneously selecting all the first group of X-lines and all the second group of Y-lines, which second aggregate memory cell current is greater than the first aggregate memory cell current; and reading the memory array by simultaneously selecting all the first group of X-lines and all the first and second groups of Y-lines and generating a signal responsive to the greater of the first and second aggregate memory cell read current.
Claim 30
Dependent Claim
13 words
The method of claim 27 wherein the memory array comprises write-once memory cells.
Claim 31
Dependent Claim
23 words
The method of claim 26 further comprising: programming more than one cell associated with an X-line by simultaneously activating at least two Y-lines.
Claim 32
Dependent Claim
19 words
The method of claim 29 wherein said at least two simultaneously activated Y-lines are associated with different Y-line groups.
Claim 33
Dependent Claim
14 words
The method of claim 26 wherein the memory array comprises passive element memory cells.
Claim 34
Dependent Claim
13 words
The method of claim 31 wherein the memory array comprises anti-fuse memory cells.
Claim 35
Dependent Claim
13 words
The method of claim 31 wherein the memory array comprises magnetoresistive memory cells.
Claim 36
Dependent Claim
13 words
The method of claim 26 wherein the memory array comprises EEPROM memory cells.
Claim 37
Dependent Claim
221 words
An integrated circuit comprising: a memory array including: a plurality of X-lines disposed on at least one layer of the memory array; a plurality of Y-lines disposed on at least one other layer of the memory array; a plurality of non-volatile memory cells, each coupled to an associated one of the plurality of X-lines and an associated one of the plurality of Y-lines; an X-line selection circuit for selecting within a first array block at least a first X-line group of at least two X-lines when in a read mode, and for selecting a lesser number of X-lines within at least the first X-line group when in a write mode; and a Y-line selection circuit for simultaneously selecting within the first array block in the read mode a first Y-line group of at least one Y-line and a second Y-line group of at least one Y-line, and for respectively coupling the selected first and second Y-line groups to respective first and second inputs of an associated sense amplifier circuit; wherein the associated sense amplifier circuit is responsive to an aggregate signal from memory cells associated with both the selected first X-line group and the selected first Y-line group, and responsive to an aggregate signal from memory cells associated with both the selected first X-line group and the selected second Y-line group.
Claim 38
Dependent Claim
221 words
An integrated circuit comprising: a memory array including: a plurality of X-lines disposed on at least one layer of the memory array; a plurality of Y-lines disposed on at least one other layer of the memory array; a plurality of non-volatile memory cells, each coupled to an associated one of the plurality of X-lines and an associated one of the plurality of Y-lines; an X-line selection circuit for selecting within a first array block at least a first X-line group of at least two X-lines when in a read mode, and for selecting a lesser number of X-lines within at least the first X-line group when in a write mode; and a Y-line selection circuit for simultaneously selecting within the first array block in the read mode a first Y-line group of at least one Y-line and a second Y-line group of at least one Y-line, and for respectively coupling the selected first and second Y-line groups to respective first and second inputs of an associated sense amplifier circuit; wherein the associated sense amplifier circuit is responsive to an aggregate signal from memory cells associated with both the selected first X-line group and the selected first Y-line group, and responsive to an aggregate signal from memory cells associated with both the selected first X-line group and the selected second Y-line group.
Claim 39
Dependent Claim
26 words
The integrated circuit as recited in claim 35 further comprising a reference signal circuit operably coupled to the second input of the associated sense amplifier circuit.
Claim 40
Dependent Claim
23 words
The integrated circuit as recited in claim 35 wherein the first Y-line group and the second Y-line group each number but one Y-line.
Claim 41
Dependent Claim
27 words
The integrated circuit as recited in claim 35 wherein the associated sense amplifier circuit is configured to sense more than two levels of aggregate memory cell signal.
Claim 42
Dependent Claim
122 words
The integrated circuit as recited in claim 35 wherein: the X-line selection circuit is further configured for selecting, when in the read mode, a second X-line group of at least two X-lines simultaneously with selecting the first X-line group; and the associated sense amplifier circuit is responsive to an aggregate signal from memory cells associated with the selected first X-line group and the selected first Y-line group and memory cells associated with the selected second X-line group and the selected first Y-line group, and responsive further to an aggregate signal from memory cells associated with the selected first X-line group and the selected second Y-line group and memory cells associated with the selected second X-line group and the selected second Y-line group.
Claim 43
Dependent Claim
40 words
The integrated circuit as recited in claim 35 wherein: the X-line selection circuit is further configured for selecting, when in the read mode, a third X-line group of at least two X-lines when the first X-line group is not selected.
Claim 44
Dependent Claim
17 words
The integrated circuit as recited in claim 35 wherein the memory array comprises passive element memory cells.
Claim 45
Dependent Claim
16 words
The integrated circuit as recited in claim 41 wherein the memory array comprises anti-fuse memory cells.
Claim 46
Dependent Claim
16 words
The integrated circuit as recited in claim 35 wherein the memory array comprises EEPROM memory cells.
Claim 47
Dependent Claim
30 words
The integrated circuit as recited in claim 35 wherein the memory array comprises a three-dimensional memory array having more than one plane of memory cells disposed above a semiconductor substrate.
Claim 48
Dependent Claim
25 words
The integrated circuit as recited in claim 44 wherein the first X-line group comprises X-lines disposed on more than one layer of the memory array.
Claim 49
Dependent Claim
25 words
The integrated circuit as recited in claim 44 wherein the first X-line group comprises X-lines disposed only on a single layer of the memory array.
Claim 50
Dependent Claim
26 words
The integrated circuit as recited in claim 35 embodied in computer readable descriptive form suitable for use in design, test or fabrication of said integrated circuit.
Claim 51
Dependent Claim
209 words
An integrated circuit comprising: a memory array including: a plurality of X-lines disposed on at least one layer of the memory array; a plurality of Y-lines disposed on at least one other layer of the memory array; a plurality of non-volatile memory cells, each coupled to an associated one of the plurality of X-lines and an associated one of the plurality of Y-lines; means for programming individual memory cells associated with a first X-line group of at least one X-line within a first array block and further associated with a first Y-line group of at least one Y-line within the first array block until a desired aggregate memory cell read current is obtained when simultaneously selecting all the first group of X-lines and all the first group of Y-lines, at least one of the first X-line group and first Y-line group including more than one such X-line or Y-line, and each of the first X-line group associated with a second Y-line group numbering at least one Y-line; and means for reading the memory array by simultaneously selecting all the first group of X-lines and all the first group of Y-lines and generating a signal responsive to the aggregate memory cell read signal conveyed on the first group of Y-lines.
Claim 52
Dependent Claim
209 words
An integrated circuit comprising: a memory array including: a plurality of X-lines disposed on at least one layer of the memory array; a plurality of Y-lines disposed on at least one other layer of the memory array; a plurality of non-volatile memory cells, each coupled to an associated one of the plurality of X-lines and an associated one of the plurality of Y-lines; means for programming individual memory cells associated with a first X-line group of at least one X-line within a first array block and further associated with a first Y-line group of at least one Y-line within the first array block until a desired aggregate memory cell read current is obtained when simultaneously selecting all the first group of X-lines and all the first group of Y-lines, at least one of the first X-line group and first Y-line group including more than one such X-line or Y-line, and each of the first X-line group associated with a second Y-line group numbering at least one Y-line; and means for reading the memory array by simultaneously selecting all the first group of X-lines and all the first group of Y-lines and generating a signal responsive to the aggregate memory cell read signal conveyed on the first group of Y-lines.
Claim 53
Dependent Claim
26 words
The integrated circuit of claim 48 further comprising: means for programming more than one cell associated with an X-line by simultaneously activating at least two Y-lines.
Claim 54
Dependent Claim
20 words
The integrated circuit of claim 49 wherein said at least two simultaneously activated Y-lines are associated with different Y-line groups.
Claim 55
Dependent Claim
15 words
The integrated circuit of claim 48 wherein the memory array comprises passive element memory cells.
Claim 56
Dependent Claim
14 words
The integrated circuit of clami 51 wherein the memory array comprises anti-fuse memory cells.
Claim 57
Dependent Claim
14 words
The integrated circuit of clami 51 wherein the memory array comprises anti-fuse memory cells.
Claim 58
Dependent Claim
14 words
The integrated circuit of claim 48 wherein the memory array comprises EEPROM memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-02-12 | 2010-08-14 | 2011-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-02-12 | 2014-08-14 | 2015-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-02-12 | 2018-08-14 | 2019-02-13 | $7700.00 | Window Closed / Lapsed |