Superconductor-semiconductor hybrid memory circuits with superconducting three-terminal switching devices

Claim 2

A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising: (a) a word-line input terminal; (b) a bit-line input terminal; (c) a first superconducting voltage controlled, three-terminal switching device, and a second superconducting voltage controlled, three-terminal switching device, each of said switching devices having a gate voltage terminal and first and second pass terminals, wherein the current flowing through each switching device via said pass terminals is controlled by the voltage applied to said gate terminal; (d) a semiconductor charge storing circuit for storing charge representing information in binary form, said semiconductor charge storing circuit having at least a first and a second output terminal; and (e) a superconducting current sensing means, said current sensing means having a biased current circuit with a bias input and a bias output, and a sensed current circuit with a sensed current input and a sensed current output; wherein said first pass terminal of said first switching device is connected to said word-line terminal; said gate terminal of said first switching device is connected to said first output terminal of said semiconductor charge storing circuit; said second pass terminal of said first switching device is connected to said sensed current input; said first pass terminal of said second switching device is connected to said word-line terminal; said gate terminal of said second switching device is connected to said second output terminal of said semiconductor charge storing circuit; said second pass terminal of said second switching device is connected to said sensed current output; and said bias input is connected to said bit-line input terminal.

Claim 3

The memory cell of claim 1, wherein said semiconductor charge storing circuit is a logic circuit being of a type that the output voltage on said first and second output terminals are logic complements.

Claim 4

The memory cell of claim 1, wherein said semiconductor charge storing circuit is a bi-stable logic circuit being of a type that the output voltage of said first and second output terminals are logic complements.

Claim 5

The memory cell of claim 1, wherein said first and second superconducting switch devices each comprise a superconducting field-effect transistor having a superconducting source, a superconducting drain, a conducting gate, and a semiconducting channel, and wherein the drain to source current is controlled by the applied gate to source voltage.

Claim 6

The memory cell of claim 1, wherein said superconducting current sensing means comprises a superconducting field-effect transistor having a superconducting source, a superconducting drain, a conducting gate, and a semiconducting channel, and wherein the drain is the sensed current input and the source is the sensed current output, and wherein the bias input is connected to said bit line and to said drain, and the bias output is connection to said source.

Claim 7

The memory cell of claim 1, wherein said superconducting current sensing means comprises a superconducting quantum interference device.

Claim 8

A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising: (a) a word-line input terminal; (b) a bit-line input terminal; (c) a first superconducting voltage controlled, three-terminal switching device, and a second superconducting voltage controlled, three-terminal switching device, each of said switching devices having a gate voltage terminal and first and second pass terminals wherein the current flowing through each switching device via said pass terminals is controlled by the voltage applied to said gate terminal, the current flow through said first switching device being biased by a gate terminal voltage the logic complement of the gate terminal voltage needed to bias current flow through said second switching device; (d) A gate terminal voltage creation means for actuating said switching devices having at least an output terminal; (e) a superconducting current sensing means, said current sensing means having a biased current circuit with a bias input and a bias output, and a sensed current circuit with a sensed current input and a sensed current output; wherein said first pass terminal of said first switching device is connected to said word-line terminal; said gate terminal of said first switching device is connected to said output terminal of said voltage creation means; said second pass terminal of said first switching device is connected to said sensed current input; said first pass terminal of said second switching device is connected to said word-line terminal; said gate terminal of said second switching device is connected to said output terminal of said voltage creation means; said second pass terminal of said second switching device is connected to said sensed current output; and said bias input is connected to said bit-line input terminal.

Claim 9

A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising: (a) a word-line input terminal; (b) a bit-line input terminal; (c) a first superconducting voltage controlled, three-terminal switching device, and a second superconducting voltage controlled, three-terminal switching device, each of said switching devices having a gate voltage terminal and first and second pass terminals wherein the current flowing through each switching device via said pass terminals is controlled by the voltage applied to said gate terminal, the current flow through said first switching device being biased by a gate terminal voltage the logic complement of the gate terminal voltage needed to bias current flow through said second switching device; (d) A gate terminal voltage creation means for actuating said switching devices having at least an output terminal; (e) a superconducting current sensing means, said current sensing means having a biased current circuit with a bias input and a bias output, and a sensed current circuit with a sensed current input and a sensed current output; wherein said first pass terminal of said first switching device is connected to said word-line terminal; said gate terminal of said first switching device is connected to said output terminal of said voltage creation means; said second pass terminal of said first switching device is connected to said sensed current input; said first pass terminal of said second switching device is connected to said word-line terminal; said gate terminal of said second switching device is connected to said output terminal of said voltage creation means; said second pass terminal of said second switching device is connected to said sensed current output; and said bias input is connected to said bit-line input terminal.

Claim 10

The memory cell of claim 7, wherein said first superconducting switch device comprises a superconducting field-effect transistor having a superconducting source, a superconducting drain, a conducting gate, and a n-doped semiconducting channel, and said second superconducting switch device comprises a superconducting field-effect transistor having a superconducting source, a superconducting drain, a conducting gate, and a p-doped semiconducting channel, wherein the drain to source current of said first switch device is biased by an applied gate to source voltage which is the logic complement of the applied gate to source voltage needed to bias the drain to source current of the second switching device.

Claim 11

The memory cell of claim 7, wherein said superconducting current sensing means comprises a superconducting field-effect transistor having a superconducting source, a superconducting drain, a conducting gate, and a semiconducting channel, and wherein the drain is the sensed current input and the source is the sensed current output, and wherein the bias input is connected to said bit line and to said drain, and the bias output is connected to said source.

Claim 12

The memory cell of claim 7, wherein said superconducting current sensing means comprises a superconducting quantum interference device.

Claim 13

The memory cell of claim 7, wherein said gate voltage creation means comprises a semiconducting field effect transistor having a semiconducting source, a semiconducting drain, a conducting gate, and a semiconducting channel, wherein the drain to source current is controlled by the applied gate to source voltage, and wherein said source is the output terminal of said gate voltage creation means.

Claim 14

A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising: (a) a word-line input terminal; (b) a bit-line input terminal; (c) a superconducting voltage controlled, three-terminal switching device, said switching device having a gate voltage terminal and first and second pass terminals wherein the current flowing through said switching device via said pass terminals is controlled by the voltage applied to said gate terminal; (d) an inductor means having an input terminal and an output terminal; (e) a gate terminal voltage creation means for actuating said switching device having at least an output terminal; (f) a superconducting current sensing means, said current sensing means having a biased current circuit with a bias input and a bias output, and a sensed current circuit with a sensed current input and a sensed current output; wherein said first pass terminal of said switching device is connected to said word-line terminal; said gate terminal of said switching device is connected to said voltage creation means; said second pass terminal of said switching device is connected to said sensed current input; said input terminal of said inductor means is connected to said word-line terminal; said output terminal of said inductor means is connected to said sensed current output; and said bias input is connected to said bit-line input terminal;

Claim 15

A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising: (a) a word-line input terminal; (b) a bit-line input terminal; (c) a superconducting voltage controlled, three-terminal switching device, said switching device having a gate voltage terminal and first and second pass terminals wherein the current flowing through said switching device via said pass terminals is controlled by the voltage applied to said gate terminal; (d) an inductor means having an input terminal and an output terminal; (e) a gate terminal voltage creation means for actuating said switching device having at least an output terminal; (f) a superconducting current sensing means, said current sensing means having a biased current circuit with a bias input and a bias output, and a sensed current circuit with a sensed current input and a sensed current output; wherein said first pass terminal of said switching device is connected to said word-line terminal; said gate terminal of said switching device is connected to said voltage creation means; said second pass terminal of said switching device is connected to said sensed current input; said input terminal of said inductor means is connected to said word-line terminal; said output terminal of said inductor means is connected to said sensed current output; and said bias input is connected to said bit-line input terminal;

Claim 16

The memory cell of claim 12, wherein said inductor means is a superconducting inductor.

Claim 17

The memory cell of claim 12, wherein said inductor means is a metallic inductor.

Claim 18

The memory cell of claim 12, wherein said superconducting switch device comprises a superconducting field-effect transistor having a superconducting source, a superconducting drain, a conducting gate, and a superconducting channel, and wherein the drain to source current is controlled by the applied gate to source voltage.

Claim 19

The memory cell of claim 12, wherein said superconducting current sensing means comprises a superconducting field-effect transistor having a superconducting source, a superconducting drain, a conducting gate, and a semiconducting channel, and wherein the drain is the sensed current input and the source is the sensed current output, and wherein the bias input is connected to said bit line and to said drain, and the bias output is connection to said source.

Claim 20

The memory cell of claim 12, wherein said superconducting current sensing means comprises a superconducting quantum interference device.

Claim 21

A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising: (a) a word-line input terminal; (b) a bit-line input terminal; (c) a first semiconducting voltage controlled, three-terminal switching device, said switching device having a gate voltage terminal and first and second pass terminals wherein the current flowing through said switching device via said pass terminals is controlled by the voltage applied to said gate terminal; (d) a capacitance means having at least a first terminal and a second terminal; and (e) a superconducting current sensing means, said current sensing means having a biased current circuit with a bias input and a bias output, and a sensed current circuit with a sensed current input and a sensed current output; wherein said gate terminal of said switching device is connected to said word-line terminal; said first pass terminal of said switching device is connected to said bit-line terminal; said second pass terminal of said switching device is connected to said first terminal of said capacitance means; said second terminal of said capacitance means is connected to electrical ground; and said bias input is connected to said bit-line input terminal.

Claim 22

A memory cell for storing and accessing information in binary form of the type useful in computer or logic circuits applications wherein a matrix comprised of a plurality of memory cells of common design is formed in row and column format, with rows being addressed via word-lines and columns being addressed via bit-lines, said cell comprising: (a) a word-line input terminal; (b) a bit-line input terminal; (c) a first semiconducting voltage controlled, three-terminal switching device, said switching device having a gate voltage terminal and first and second pass terminals wherein the current flowing through said switching device via said pass terminals is controlled by the voltage applied to said gate terminal; (d) a capacitance means having at least a first terminal and a second terminal; and (e) a superconducting current sensing means, said current sensing means having a biased current circuit with a bias input and a bias output, and a sensed current circuit with a sensed current input and a sensed current output; wherein said gate terminal of said switching device is connected to said word-line terminal; said first pass terminal of said switching device is connected to said bit-line terminal; said second pass terminal of said switching device is connected to said first terminal of said capacitance means; said second terminal of said capacitance means is connected to electrical ground; and said bias input is connected to said bit-line input terminal.

Claim 23

The memory cell of claim 18, wherein said capacitance means is the gate to source capacitance of a second semiconducting voltage controlled, three terminal switching device, said switching device having a gate voltage terminal and first and second pass terminals wherein the current flowing through said switching device via said pass terminals is controlled by the voltage applied to gate terminals and wherein said first pass terminal of said second switching device is connected to said second pass terminal of said first switching device, said gate terminal is the first terminal of said capacitance means of said capacitance means and said second terminal is said second pass terminal of said second semiconducting device.

Claim 24

The memory cell of claim 18, further comprising a gate terminal voltage creation means having at least an output terminal, wherein said output terminal is connected to said first terminal of said capacitance means.

Claim 25

The memory of claim 18, wherein said gate voltage creation means comprises a semiconducting field effect transistor having a semiconducting source, a semiconducting drain, a conducting gate, and a semiconducting channel, wherein the drain to source current is controlled by the applied gate to source voltage, and wherein said source is the output terminal of said gate voltage creation means.

Claim 26

The memory cell of claim 18, wherein said superconducting current sensing means comprises a superconducting field-effect transistor having a superconducting source, a superconducting drain, a conducting gate, and a semiconducting channel, and wherein the drain is the sensed current input and the source is the sensed current output, and wherein the bias input is connected to said bit line and to said drain, and the bias output is connection to said source.

Claim 27

The memory cell of claim 18, wherein said superconducting current sensing means comprises a superconducting quantum interference device.

Claim 28

The memory cell of claim 18, wherein said superconducting current sensing means comprises a rapid single flux quantum current sensing buffer/amplifier circuit.

Claim 29

The memory cell of claim 18, wherein said superconducting current sensing means comprises a superconductor link circuit.

Claim 30

The memory cell of claim 18, wherein said current sensing means further comprises a self-timing means comprising a voltage controlled three-terminal switching device having a gate voltage terminal and first and second pass terminals, wherein the current flowing through said switching device via said pass terminals is controlled by the voltage applied to said gate terminal, and wherein said gate terminal is connected to a self-timed signal, said first pass terminal is connected to said bias input and said second pass terminal is connected to said sensed current input.

Claim 31

The memory cell of claim 18, further comprising: a data-in terminal; a second voltage controlled three-terminal switching device comprising a gate voltage terminal and first and second pass terminals, wherein the current flowing through said switching device via said pass terminals is controlled by the voltage applied to said gate terminal; a voltage source; and a superconductor switching device having at least a first and second terminal; wherein said data-in terminal is connected to said gate terminal of said second switching device; said first pass terminal is connected to said voltage source; said second pass terminal of said second switching device is connected to said first terminal of said superconductor switching device; said second terminal of said superconductor switching device is connected to said first pass terminal of said first switching device.

Claim 32

The memory cell of claim 27, wherein said superconductor switching device is a stack of Josephson junction devices.

Claim 33

The memory cell of claim 27, wherein said superconductor switching device is a superconducting link.

Claim 34

The memory cell of claim 27, wherein said superconductor switching device is voltage controlled superconducting field-effect transistor having a conducting gate, a superconducting source and a superconducting drain, wherein the drain to source current is controlled by the applied gate to source voltage and wherein said gate is connected to said data-in terminal, said drain is connected to said second pass terminal of said second switching device, and said source is connected to said first terminal of said first switching device.