US6780711B2
Expired / Lapsed
US
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Vertically stacked field programmable nonvolatile memory and method of fabrication
Assignee: SanDisk Technologies LLC
•
Filing: 2002-09-23
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Granted: 2004-08-24
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Expires: 2022-09-23
Abstract
Abstract A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
Inventors
- 👤 Mark G. Johnson
- 👤 Thomas H. Lee
- 👤 Vivek Subramanian
- 👤 Paul Michael Farmwald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:07
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/06; G11C11/00; G11C11/56; G11C11/5692; G11C13/00; G11C13/0002; G11C13/0021; G11C13/003; G11C17/14; G11C17/16; G11C17/165; H; H10; H10B; H10B63/00; H10B63/80; H10B63/84; H10N; H10N70/00; H10N70/011; H10N70/801; H10N70/821; H10N70/826; G11C2213/00; G11C2213/70; G11C2213/71; G11C2213/76
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
107 words
A method of fabricating a memory array comprising: forming a first conductor level of spaced-apart, parallel, generally coplanar conductors extending in a first direction; depositing a layer stack, then patterning and etching said layer stack to form a first pillar level of pillars, forming a second conductor level of spaced-apart, parallel, generally coplanar conductors above the first pillar level, the conductors of said second conductor level extending in a second direction, said second direction not parallel to said first direction, wherein the pillars of the first pillar level are vertically disposed between the conductors of the first conductor level and the conductors of the second conductor level.
Claim 2
Independent Claim
107 words
A method of fabricating a memory array comprising: forming a first conductor level of spaced-apart, parallel, generally coplanar conductors extending in a first direction; depositing a layer stack, then patterning and etching said layer stack to form a first pillar level of pillars, forming a second conductor level of spaced-apart, parallel, generally coplanar conductors above the first pillar level, the conductors of said second conductor level extending in a second direction, said second direction not parallel to said first direction, wherein the pillars of the first pillar level are vertically disposed between the conductors of the first conductor level and the conductors of the second conductor level.
Claim 3
Dependent Claim
25 words
The method of claim 1 , further comprising: following the step of forming the first pillar level of pillars, depositing and planarizing an insulating material.
Claim 4
Dependent Claim
13 words
The method of claim 1 , wherein the pillars comprise a state-change element.
Claim 5
Dependent Claim
13 words
The method of claim 1 , wherein the pillars comprise a steering element.
Claim 6
Dependent Claim
15 words
The method of claim 1 , wherein the memory array is a write-once memory array.
Claim 7
Dependent Claim
18 words
The method of claim 1 wherein any of the conductors comprises one or more of tungsten and aluminum.
Claim 8
Dependent Claim
25 words
The method of claim 6 , wherein the memory array comprises a barrier material of one or more of: titanium nitride, tantalum and tantalum nitride.
Claim 9
Dependent Claim
13 words
The method of claim 1 wherein any of the pillars comprises an antifuse.
Claim 10
Dependent Claim
11 words
The method of claim 8 wherein the antifuse comprises silicon dioxide.
Claim 11
Dependent Claim
109 words
A memory array created by a method, the method comprising: forming a first conductor level of spaced-apart, parallel, generally coplanar conductors extending in a first direction; depositing a layer stack, then patterning and etching said layer stack to form a first pillar level of pillars; forming a second conductor level of spaced-apart, parallel, generally coplanar conductors above the first pillar level, the conductors of said second conductor level extending in a second direction, said second direction not parallel to said first direction, wherein the pillars of the first pillar level are vertically disposed between the conductors of the first conductor level and the conductors of the second conductor level.
Claim 12
Dependent Claim
109 words
A memory array created by a method, the method comprising: forming a first conductor level of spaced-apart, parallel, generally coplanar conductors extending in a first direction; depositing a layer stack, then patterning and etching said layer stack to form a first pillar level of pillars; forming a second conductor level of spaced-apart, parallel, generally coplanar conductors above the first pillar level, the conductors of said second conductor level extending in a second direction, said second direction not parallel to said first direction, wherein the pillars of the first pillar level are vertically disposed between the conductors of the first conductor level and the conductors of the second conductor level.
Claim 13
Dependent Claim
25 words
The memory array of claim 10 further comprising: following the step of forming the first pillar level of pillars, depositing and planarizing an insulating material.
Claim 14
Dependent Claim
14 words
The memory array of claim 10 , wherein the pillars comprise a state-change element.
Claim 15
Dependent Claim
14 words
The memory array of claim 10 , wherein the pillars comprise a steering element.
Claim 16
Dependent Claim
16 words
The memory array of claim 10 , wherein the memory array is a write-once memory array.
Claim 17
Dependent Claim
20 words
The memory array of claim 10 , wherein any of the conductors comprises one or more of tungsten and aluminum.
Claim 18
Dependent Claim
26 words
The memory array of claim 15 , wherein the memory array comprises a barrier material of one or more of titanium nitride, tantalum and tantalum nitride.
Claim 19
Dependent Claim
14 words
The memory array of claim 10 wherein any of the pillars comprises an antifuse.
Claim 20
Dependent Claim
12 words
The memory array of claim 17 wherein the antifuse comprises silicon dioxide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-08-24 | 2008-02-23 | 2008-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-08-24 | 2012-02-23 | 2012-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-08-24 | 2016-02-23 | 2016-08-24 | $7700.00 | Window Closed / Lapsed |