US6879505B2 — Word line arrangement having multi-layer word lin…

Claim 1

Independent Claim 90 words

An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer.

Claim 2

Dependent Claim 90 words

An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer.

Claim 3

Dependent Claim 33 words

The integrated circuit of claim 1 wherein each respective word line comprises at least one word line segment on each word line layer connected together by way of a respective single vertical connection.

Claim 4

Dependent Claim 10 words

The integrated circuit of claim 1 comprising anti-fuse memory cells.

Claim 5

Dependent Claim 10 words

The integrated circuit of claim 1 comprising fuse memory cells.

Claim 6

Dependent Claim 28 words

The integrated circuit of claim 1 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

Claim 7

Dependent Claim 28 words

The integrated circuit of claim 5 wherein at most one memory cell of a simultaneously programmed group of memory cells is coupled to an individual word line segment.

Claim 8

Dependent Claim 26 words

The integrated circuit of claim 5 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

Claim 9

Dependent Claim 30 words

The integrated circuit of claim 1 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

Claim 10

Dependent Claim 27 words

The integrated circuit of claim 1 wherein the memory array comprises a plurality of array blocks and the word line segments in each array block are interleaved.

Claim 11

Dependent Claim 30 words

The integrated circuit of claim 9 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

Claim 12

Dependent Claim 49 words

The integrated circuit of claim 9 further comprising a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

Claim 13

Dependent Claim 32 words

The integrated circuit of claim 11 including word lines respectively comprising at least one word line segment on each word line layer connected together by way of a respective single vertical connection.

Claim 14

Dependent Claim 28 words

The integrated circuit of claim 12 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

Claim 15

Dependent Claim 26 words

The integrated circuit of claim 13 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

Claim 16

Dependent Claim 28 words

The integrated circuit of claim 1 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

Claim 17

Dependent Claim 26 words

The integrated circuit of claim 15 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

Claim 18

Dependent Claim 49 words

The integrated circuit of claim 1 further comprising a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

Claim 19

Dependent Claim 57 words

The integrated circuit of claim 17 wherein: each block includes a respective plurality of N selected bias lines; and each select node of the multi-headed word line decoder circuit is coupled to a respective group of N word line driver circuits associated with a block, each coupled to a respective one of the N selected bias lines.

Claim 20

Dependent Claim 58 words

The integrated circuit of claim 18 wherein each respective selected bias line is operably driven to a selected bias level by a respective first circuit arranged to initially drive the line from an unselected bias level toward the selected bias level, and by a second circuit for subsequently providing a lower impedance path to the selected bias level.

Claim 21

Dependent Claim 39 words

The integrated circuit of claim 19 wherein the respective second circuit for each respective selected bias line comprises a plurality of spatially distributed circuits operably coupling the respective selected bias line to a source of the selected bias level.

Claim 22

Dependent Claim 26 words

The integrated circuit of claim 18 wherein each memory block includes an unselected bias line shared by all word line driver circuits associated with the block.

Claim 23

Dependent Claim 17 words

The integrated circuit of claim 1 wherein each of said bit lines traverses across an array block.

Claim 24

Dependent Claim 30 words

The integrated circuit of claim 1 wherein each of said bit lines is segmented, being operably coupled to an associated global bit line disposed on another layer of the array.

Claim 25

Dependent Claim 42 words

An integrated circuit comprising a three-dimensional programmable memory array having at least two word line layers, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on every word line layer.

Claim 26

Dependent Claim 42 words

An integrated circuit comprising a three-dimensional programmable memory array having at least two word line layers, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on every word line layer.

Claim 27

Dependent Claim 17 words

The integrated circuit of claim 24 wherein the memory array comprises a passive element memory cell array.

Claim 28

Dependent Claim 52 words

The integrated circuit of claim 25 wherein the memory array comprises memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer.

Claim 29

Dependent Claim 49 words

The integrated circuit of claim 24 further comprising a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

Claim 30

Dependent Claim 25 words

The integrated circuit of claim 24 wherein all word line segments for each respective word line are connected together by a respective single vertical connection.

Claim 31

Dependent Claim 25 words

The integrated circuit of claim 28 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array.

Claim 32

Dependent Claim 17 words

The integrated circuit of claim 28 wherein the word line segments in each array block are interleaved.

Claim 33

Dependent Claim 30 words

The integrated circuit of claim 30 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

Claim 34

Dependent Claim 28 words

The integrated circuit of claim 28 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

Claim 35

Dependent Claim 28 words

The integrated circuit of claim 32 wherein at most one memory cell of a simultaneously programmed group of memory cells is coupled to an individual word line segment.

Claim 36

Dependent Claim 26 words

The integrated circuit of claim 32 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

Claim 37

Independent Claim 171 words

A method for programming a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer, said method comprising the steps of: selecting a word line in the array; selecting at least two bit lines associated with the selected word line; coupling the selected word line to a source of a suitable programming bias level; coupling each of the selected bit lines to either a suitable programming bias level or an inhibit bias level in accordance with a respective data bit to be programmed, to thereby simultaneously program multiple memory cells coupled to the selected word line.

Claim 38

Independent Claim 171 words

A method for programming a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer, said method comprising the steps of: selecting a word line in the array; selecting at least two bit lines associated with the selected word line; coupling the selected word line to a source of a suitable programming bias level; coupling each of the selected bit lines to either a suitable programming bias level or an inhibit bias level in accordance with a respective data bit to be programmed, to thereby simultaneously program multiple memory cells coupled to the selected word line.

Claim 39

Dependent Claim 24 words

The method of claim 35 wherein each simultaneously programmed memory cell is associated with a different word line segment of the selected word line.

Claim 40

Dependent Claim 99 words

A computer readable medium encoding an integrated circuit, said encoded integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer.

Claim 41

Dependent Claim 99 words

A computer readable medium encoding an integrated circuit, said encoded integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer.

Claim 42

Dependent Claim 34 words

The computer readable medium of claim 37 wherein each respective word line comprises at least one word line segment on each word line layer connected together by way of a respective single vertical connection.

Claim 43

Dependent Claim 16 words

The computer readable medium of claim 37 wherein the encoded integrated circuit comprises anti-fuse memory cells.

Claim 44

Dependent Claim 16 words

The computer readable medium of claim 37 wherein the encoded integrated circuit comprises fuse memory cells.

Claim 45

Dependent Claim 29 words

The computer readable medium of claim 37 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

Claim 46

Dependent Claim 39 words

The integrated circuit of claim 25 wherein the memory array comprises memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on at least one associated bit line layer.

Claim 47

Dependent Claim 22 words

The method of claim 35 wherein the simultaneously programmed memory cells include at least two associated with a single bit line layer.

Claim 48

Dependent Claim 13 words

The method of claim 34 wherein the memory cells compromise anti-fuse memory cells.

Claim 49

Dependent Claim 30 words

The method of claim 35 wherein coupling the selected word line comprises driving the selected word line by an N-channel transistor to the source of the suitable programming bias level.

Claim 50

Dependent Claim 79 words

The method of claim 35 wherein coupling the selected word line comprises: driving the selected word line to a selected bias line; and driving the selected bias line to the source of the suitable programming bias level by a respective first circuit arranged to initially drive the selected bias line from an unselected bias level toward the suitable programming bias level, and by a second circuit for subsequently providing a lower impedance path to a suitable programming bias level.

Claim 51

Dependent Claim 16 words

The method of claim 46 wherein the second circuit comprises a plurality of spatially distributed circuits.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2008-04-11	2008-10-11	2009-04-12	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2012-04-11	2012-10-11	2013-04-12	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2016-04-11	2016-10-11	2017-04-12	$7700.00	Window Closed / Lapsed

Word line arrangement having multi-layer word line segments for three-dimensional memory array

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