US6822903B2
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Apparatus and method for disturb-free programming of passive element memory cells
Assignee: SanDisk Technologies LLC
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Filing: 2003-03-31
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Granted: 2004-11-23
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Expires: 2023-03-31
Abstract
Abstract In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.
Inventors
- 👤 Roy E. Scheuerlein
- 👤 N. Johan Knall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:10
CPC Classifications
G; G11; G11C; G11C13/00; G11C13/0002; G11C13/0009; G11C13/0014; B; B82; B82Y; B82Y10/00; G11C17/00; G11C17/14; G11C17/16; G11C17/165; G11C2213/00; G11C2213/70; G11C2213/71; G11C2213/72
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
185 words
A method for programming a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode of anode regions being configured to inject charge to the other region when forward biased, said method comprising: driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line; and driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the first array line; then driving the first array line to an unselected bias voltage for the first array line; and driving the second array line to an unselected bias voltage for the second array line wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage.
Claim 2
Independent Claim
185 words
A method for programming a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode of anode regions being configured to inject charge to the other region when forward biased, said method comprising: driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line; and driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the first array line; then driving the first array line to an unselected bias voltage for the first array line; and driving the second array line to an unselected bias voltage for the second array line wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage.
Claim 3
Dependent Claim
26 words
The method of claim 1 wherein the memory array comprises a three-dimensional array having at least three array line layers defining at least two memory planes.
Claim 4
Dependent Claim
33 words
The method of claim 2 wherein the memory array comprises memory cells whose anode region is alternately an upper region of some memory layers and a lower region of vertically adjacent memory layers.
Claim 5
Dependent Claim
32 words
The method of claim 2 wherein the memory array comprises memory cells whose anode region is either an upper region of all memory layers, or a lower region of all memory layers.
Claim 6
Dependent Claim
13 words
The method of claim 1 wherein the memory array comprises antifuse memory cells.
Claim 7
Dependent Claim
107 words
The method of claim 5 wherein the memory array includes memory cells respectively comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of array lines on a first associated array line layer, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of array lines on a second associated array line layer, said second semiconductor region being more lightly doped than the first semiconductor region, said non-injecting region comprising the second semiconductor region, and said injecting region comprising the first semiconductor region.
Claim 8
Dependent Claim
17 words
The method of claim 6 wherein the second semiconductor region comprises a lightly-doped n-type (n−) semiconductor region.
Claim 9
Dependent Claim
17 words
The method of claim 6 wherein the second semiconductor region comprises a lightly-doped p-type (p−) semiconductor region.
Claim 10
Dependent Claim
17 words
The method of claim 6 wherein the second semiconductor region is initially formed as an intrinsic region.
Claim 11
Dependent Claim
13 words
The method of claim 1 wherein the memory array comprises fuse memory cells.
Claim 12
Dependent Claim
16 words
The method of claim 1 wherein the memory array comprises memory cells including a ferro-electric material.
Claim 13
Dependent Claim
16 words
The method of claim 1 wherein the memory array comprises memory cells including an organic layer.
Claim 14
Dependent Claim
23 words
The method of claim 1 wherein said non-injecting regions comprise lightly-doped semiconductor regions, and said injecting regions comprise more heavily doped semiconductor regions.
Claim 15
Dependent Claim
20 words
The method of claim 1 wherein said non-injecting regions comprise lightly-doped semiconductor regions, and said injecting regions comprise a metal.
Claim 16
Dependent Claim
19 words
The method of claim 1 wherein: the first percentage comprises around 50%; and the second percentage comprises around 50%.
Claim 17
Dependent Claim
19 words
The method of claim 1 wherein: the first percentage comprises around 90%; and the second percentage comprises around 10%.
Claim 18
Dependent Claim
37 words
The method claim 1 wherein the second array line voltage transitions at least a third percentage toward its selected bias voltage before the first array line transitions at most a fourth percentage toward its selected bias voltage.
Claim 19
Dependent Claim
19 words
The method of claim 17 wherein: the third percentage comprises around 50%; and the fourth percentage comprises around 50%.
Claim 20
Dependent Claim
19 words
The method of claim 17 wherein: the third percentage comprises around 90%; and the fourth percentage comprises around 10%.
Claim 21
Dependent Claim
36 words
The method of claim 1 wherein each array line associated with a memory cell non-injecting region comprises a continuous semiconductor layer that forms a portion of the respective non-injecting region of respective memory cells associated therewith.
Claim 22
Dependent Claim
48 words
The method of claim 1 wherein each array line associated with a memory cell non-injecting region comprises a continuous semiconductor layer that connects to the respective non-injecting region of respective memory cells associated therewith, wherein the continuous semiconductor layer and the non-injecting regions have a different doping density.
Claim 23
Dependent Claim
17 words
The method of claim 20 wherein the array comprises at least one layer of rail-stack array lines.
Claim 24
Dependent Claim
16 words
The method of claim 22 wherein the rail-stack array lines include a conductor comprising a metal.
Claim 25
Dependent Claim
195 words
An integrated circuit comprising: a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode or anode regions being configured to inject charge to the other region when forward biased; and array support circuitry configured, when in a programming mode, for driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line, for driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the second array line, and for then driving the first array line to an unselected bias voltage for the first array line, and driving the second array line to an unselected bias voltage for the second array line, wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage.
Claim 26
Dependent Claim
195 words
An integrated circuit comprising: a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode or anode regions being configured to inject charge to the other region when forward biased; and array support circuitry configured, when in a programming mode, for driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line, for driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the second array line, and for then driving the first array line to an unselected bias voltage for the first array line, and driving the second array line to an unselected bias voltage for the second array line, wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage.
Claim 27
Dependent Claim
27 words
The integrated circuit of claim 24 wherein the memory array comprises a three-dimensional array having at least three array line layers defining at least two memory planes.
Claim 28
Dependent Claim
34 words
The integrated circuit of claim 25 wherein the memory array comprises memory cells whose anode region is alternately an upper region of some memory layers and a lower region of vertically adjacent memory layers.
Claim 29
Dependent Claim
33 words
The integrated circuit of claim 25 wherein the memory array comprises memory cells whose anode region is either an upper region of all memory layers, or a lower region of all memory layers.
Claim 30
Dependent Claim
14 words
The integrated circuit of claim 24 wherein the memory array comprises antifuse memory cells.
Claim 31
Dependent Claim
108 words
The integrated circuit of claim 28 wherein the memory array includes memory cells respectively comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of array lines on a first associated array line layer, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of array lines on a second associated array line layer, said second semiconductor region being more lightly doped than the first semiconductor region, said non-injecting region comprising the second semiconductor region, and said injecting region comprising the first semiconductor region.
Claim 32
Dependent Claim
18 words
The integrated circuit of claim 29 wherein the second semiconductor region comprises a lightly-doped n-type (n−) semiconductor region.
Claim 33
Dependent Claim
18 words
The integrated circuit of claim 29 wherein the second semiconductor region comprises a lightly-doped p-type (p−) semiconductor region.
Claim 34
Dependent Claim
18 words
The integrated circuit of claim 29 wherein the second semiconductor region is initially formed as an intrinsic region.
Claim 35
Dependent Claim
14 words
The integrated circuit of claim 24 wherein the memory array comprises fuse memory cells.
Claim 36
Dependent Claim
17 words
The integrated circuit of claim 24 wherein the memory array comprises memory cells including a ferro-electric material.
Claim 37
Dependent Claim
17 words
The integrated circuit of claim 24 wherein the memory array comprises memory cells including an organic layer.
Claim 38
Dependent Claim
24 words
The integrated circuit of claim 24 wherein said non-injecting regions comprise lightly-doped semiconductor regions, and said injecting regions comprise more heavily doped semiconductor regions.
Claim 39
Dependent Claim
21 words
The integrated circuit of claim 24 wherein said non-injecting regions comprise lightly-doped semiconductor regions, and said injecting regions comprise a metal.
Claim 40
Dependent Claim
20 words
The integrated circuit of claim 24 wherein: the first percentage comprises around 50%; and the second percentage comprises around 50%.
Claim 41
Dependent Claim
20 words
The integrated circuit of claim 24 wherein: the first percentage comprises around 90%; and the second percentage comprises around 10%.
Claim 42
Dependent Claim
38 words
The integrated circuit claim 24 wherein the second array line voltage transitions at least a third percentage toward its selected bias voltage before the first array line transitions at most a fourth percentage toward its selected bias voltage.
Claim 43
Dependent Claim
20 words
The integrated circuit of claim 40 wherein: the third percentage comprises around 50%; and the fourth percentage comprises around 50%.
Claim 44
Dependent Claim
20 words
The integrated circuit of claim 40 wherein: the third percentage comprises around 90%; and the fourth percentage comprises around 10%.
Claim 45
Dependent Claim
37 words
The integrated circuit of claim 24 wherein each array line associated with a memory cell non-injecting region comprises a continuous semiconductor layer that forms a portion of the respective non-injecting region of respective memory cells associated therewith.
Claim 46
Dependent Claim
49 words
The integrated circuit of claim 24 wherein each array line associated with a memory cell non-injecting region comprises a continuous semiconductor layer that connects to the respective non-injecting region of respective memory cells associated therewith, wherein the continuous semiconductor layer and the non-injecting regions have a different doping density.
Claim 47
Dependent Claim
18 words
The integrated circuit of claim 43 wherein the array comprises at least one layer of rail-stack array lines.
Claim 48
Dependent Claim
17 words
The integrated circuit of claim 45 wherein the rail-stack array lines include a conductor comprising a metal.
Claim 49
Dependent Claim
18 words
A computer readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 24 .
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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