US7106652B2 — Word line arrangement having multi-layer word lin…

Claim 1

Independent Claim 63 words

An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each word line being operably coupled to an associated selected bias line traversing perpendicular to the word line segments.

Claim 2

Dependent Claim 63 words

An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each word line being operably coupled to an associated selected bias line traversing perpendicular to the word line segments.

Claim 3

Dependent Claim 60 words

The integrated circuit of claim 1 further comprising at least three word line layers, wherein at least some segmented word lines comprise connected-together word line segments on a first group of one or more word line layers, and at least some segmented word lines comprise connected-together word line segments on a second group of one or more word line layers.

Claim 4

Dependent Claim 49 words

The integrated circuit of claim 1 further comprising a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

Claim 5

Dependent Claim 28 words

The integrated circuit of claim 3 wherein each select node traverses across at least a portion of the array on an interconnect layer disposed beneath the memory array.

Claim 6

Dependent Claim 25 words

The integrated circuit of claim 1 wherein all word line segments for each respective word line are connected together by a respective single vertical connection.

Claim 7

Dependent Claim 25 words

The integrated circuit of claim 5 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array.

Claim 8

Dependent Claim 17 words

The integrated circuit of claim 5 wherein the word line segments in each array block are interleaved.

Claim 9

Dependent Claim 30 words

The integrated circuit of claim 7 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

Claim 10

Dependent Claim 28 words

The integrated circuit of claim 5 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

Claim 11

Dependent Claim 28 words

The integrated circuit of claim 9 wherein at most one memory cell of a simultaneously programmed group of memory cells is associated with an individual word line segment.

Claim 12

Dependent Claim 26 words

The integrated circuit of claim 9 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

Claim 13

Dependent Claim 77 words

The integrated circuit of claim 1 wherein: the memory array is organized as a plurality of blocks; each block includes a respective plurality of N selected bias lines; and the integrated circuit further comprises a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of N word line driver circuits associated with a block, each coupled to a respective one of the N selected bias lines.

Claim 14

Dependent Claim 58 words

The integrated circuit of claim 12 wherein each respective selected bias line is operably driven to a selected bias level by a respective first circuit arranged to initially drive the line from an unselected bias level toward the selected bias level, and by a second circuit for subsequently providing a lower impedance path to the selected bias level.

Claim 15

Dependent Claim 39 words

The integrated circuit of claim 13 wherein the respective second circuit for each respective selected bias line comprises a plurality of spatially distributed circuits operably coupling the respective selected bias line to a source of the selected bias level.

Claim 16

Dependent Claim 29 words

The integrated circuit of claim 13 wherein a given memory block includes an unselected bias line shared by all word line driver circuits associated with the given memory block.

Claim 17

Dependent Claim 10 words

The integrated circuit of claim 1 comprising antifuse memory cells.

Claim 18

Dependent Claim 18 words

A computer readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 1 .

Claim 19

Independent Claim 212 words

A method for programming a three-dimensional passive element memory cell array, said method comprising the steps of: selecting a block of the memory array, each block comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each block further including a respective plurality of N selected bias lines traversing perpendicular to the word line segments; selecting one of a plurality of select nodes of a multi-headed word line decoder circuit, each select node being coupled to a respective group of N word line driver circuits associated with the selected block, each word line driver circuit coupled to a respective one of the N selected bias lines for the selected block; driving one of the N selected bias lines for the selected block to a selected bias level, thereby coupling a selected word line to a source of a suitable programming bias level; and coupling a selected bit line in the selected block to either a suitable programming bias level or an inhibit bias level in accordance with a respective data bit to be programmed, to thereby program a selected memory cell coupled between the selected bit line and the selected word line.

Claim 20

Independent Claim 212 words

A method for programming a three-dimensional passive element memory cell array, said method comprising the steps of: selecting a block of the memory array, each block comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each block further including a respective plurality of N selected bias lines traversing perpendicular to the word line segments; selecting one of a plurality of select nodes of a multi-headed word line decoder circuit, each select node being coupled to a respective group of N word line driver circuits associated with the selected block, each word line driver circuit coupled to a respective one of the N selected bias lines for the selected block; driving one of the N selected bias lines for the selected block to a selected bias level, thereby coupling a selected word line to a source of a suitable programming bias level; and coupling a selected bit line in the selected block to either a suitable programming bias level or an inhibit bias level in accordance with a respective data bit to be programmed, to thereby program a selected memory cell coupled between the selected bit line and the selected word line.

Claim 21

Dependent Claim 56 words

The method as recited in claim 18 wherein said one of the N selected bias lines is driven by a first circuit arranged to initially drive the bias line from an unselected bias level toward the selected bias level, and by a second circuit for subsequently providing a lower impedance path to the selected bias level.

Claim 22

Dependent Claim 61 words

The method as recited in claim 18 further comprising coupling a second selected bit line in the selected block to either a suitable programming bias level or an inhibit bias level in accordance with a respective data bit to be programmed, to thereby program a second selected memory cell coupled between the second selected bit line and the selected word line.

Claim 23

Dependent Claim 104 words

An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each word line being operably coupled to an associated selected bias line by a multi-headed decoder circuit, said decoder circuit comprising a plurality of select nodes routed on a layer beneath the memory array and coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

Claim 24

Dependent Claim 104 words

An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each word line being operably coupled to an associated selected bias line by a multi-headed decoder circuit, said decoder circuit comprising a plurality of select nodes routed on a layer beneath the memory array and coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

Claim 25

Dependent Claim 60 words

The integrated circuit of claim 21 further comprising at least three word line layers, wherein at least some segmented word lines comprise connected-together word line segments on a first group of one or more word line layers, and at least some segmented word lines comprise connected-together word line segments on a second group of one or more word line layers.

Claim 26

Dependent Claim 54 words

The integrated circuit of claim 21 wherein the memory array comprises memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of at least one associated bit line layer, each bit line layer being associated with at most one word line layer.

Claim 27

Dependent Claim 25 words

The integrated circuit of claim 21 wherein all word line segments for each respective word line are connected together by a respective single vertical connection.

Claim 28

Dependent Claim 25 words

The integrated circuit of claim 24 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array.

Claim 29

Dependent Claim 23 words

The integrated circuit of claim 24 wherein the word line segments on a given word line layer in each array block are interleaved.

Claim 30

Dependent Claim 30 words

The integrated circuit of claim 26 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

Claim 31

Dependent Claim 59 words

The integrated circuit of claim 21 wherein: each memory array block includes a respective plurality of N selected bias lines; and each select node of the multi-headed word line decoder circuit is coupled to a respective group of N word line driver circuits associated with a block, each coupled to a respective one of the N selected bias lines.

Claim 32

Dependent Claim 8 words

The integrated circuit of claim 28 wherein N=>1.

Claim 33

Dependent Claim 8 words

The integrated circuit of claim 29 wherein N=>2.

Claim 34

Dependent Claim 8 words

The integrated circuit of claim 30 wherein N=4.

Claim 35

Dependent Claim 58 words

The integrated circuit of claim 28 wherein each respective selected bias line is operably driven to a selected bias level by a respective first circuit arranged to initially drive the line from an unselected bias level toward the selected bias level, and by a second circuit for subsequently providing a lower impedance path to the selected bias level.

Claim 36

Dependent Claim 39 words

The integrated circuit of claim 32 wherein the respective second circuit for each respective selected bias line comprises a plurality of spatially distributed circuits operably coupling the respective selected bias line to a source of the selected bias level.

Claim 37

Dependent Claim 26 words

The integrated circuit of claim 28 wherein each memory block includes an unselected bias line shared by all word line driver circuits associated with the block.

Claim 38

Dependent Claim 10 words

The integrated circuit of claim 21 comprising antifuse memory cells.

Claim 39

Dependent Claim 18 words

A computer readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 21 .

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2009-09-11	2010-03-13	2010-09-12	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2013-09-11	2014-03-13	2014-09-12	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2017-09-11	2018-03-13	2018-09-12	$7700.00	Window Closed / Lapsed

Word line arrangement having multi-layer word line segments for three-dimensional memory array

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