US7023739B2
Expired / Lapsed
US
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NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
Assignee: SanDisk Technologies LLC
•
Filing: 2003-12-05
•
Granted: 2006-04-04
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Expires: 2023-12-05
Abstract
Abstract An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
Inventors
- 👤 En-Hsing Chen
- 👤 Andrew J. Walker
- 👤 Roy E. Scheuerlein
- 👤 Sucheta Nallamothu
- 👤 Alper Ilkbahar
- 👤 Luca G. Fasoli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:50
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C11/00; G11C11/56; G11C11/5671; G11C16/04; G11C16/0483; G11C16/12; G11C16/0466
Claims Analysis
Total Claims: 98
Claim 1
Independent Claim
94 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said modifiable conductance switch devices comprising thin film transistor (TFT) devices, said method comprising pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block.
Claim 2
Independent Claim
94 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said modifiable conductance switch devices comprising thin film transistor (TFT) devices, said method comprising pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block.
Claim 3
Dependent Claim
18 words
The method of claim 1 further comprising performing a read operation only after at least two programming pulses.
Claim 4
Dependent Claim
18 words
The method of claim 1 further comprising maintaining an inhibit voltage on associated array lines between programming pulses.
Claim 5
Dependent Claim
34 words
The method of claim 1 wherein the leakage current effects include changes in a voltage bias at one or more locations within a NAND string that otherwise may occur during a long programming pulse.
Claim 6
Dependent Claim
27 words
The method of claim 4 further comprising re-establishing a respective bias condition within selected and unselected NAND strings of a selected block before each such programming pulse.
Claim 7
Independent Claim
123 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising: pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage; and de-coupling unselected NAND strings within the selected memory block from other associated array lines conveying bias voltages other than the inhibit voltage.
Claim 8
Independent Claim
123 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising: pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage; and de-coupling unselected NAND strings within the selected memory block from other associated array lines conveying bias voltages other than the inhibit voltage.
Claim 9
Dependent Claim
19 words
The method of claim 6 further comprising maintaining the inhibit voltage on the associated array lines between programming pulses.
Claim 10
Dependent Claim
60 words
The method of claim 6 further comprising: driving the selected word line to a voltage less than the programming voltage while unselected NAND strings are coupled to the associated array lines conveying the inhibit voltage; then decoupling the unselected NAND strings from the associated array lines conveying the inhibit voltage; and pulsing the selected word line to the programming voltage.
Claim 11
Dependent Claim
35 words
The method of claim 8 wherein: the selected word line is brought to ground before decoupling unselected NAND strings from the associated array lines conveying the inhibit voltage, and then driven to the programming voltage.
Claim 12
Dependent Claim
33 words
The method of claim 6 wherein the de-coupling unselected NAND strings step comprises turning off at least one of a plurality of series select devices at an end of the selected NAND strings.
Claim 13
Dependent Claim
24 words
The method of claim 10 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.
Claim 14
Dependent Claim
57 words
The method of claim 1 further comprising: coupling the selected NAND string to an associated array line conveying one of either a bit line programming voltage to program the selected memory cell or a bit line inhibit voltage to inhibit programming of the selected memory cell; and de-coupling the selected NAND string from other associated array lines.
Claim 15
Dependent Claim
34 words
The method of claim 12 wherein the de-coupling the selected NAND string step comprises turning off at least one of a plurality of series select devices at an end of the selected NAND strings.
Claim 16
Dependent Claim
24 words
The method of claim 13 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.
Claim 17
Dependent Claim
40 words
The method of claim 13 wherein the turning off step comprises driving to different levels respective select signals corresponding to at least two respective ones of the plurality of series select devices at the end of the selected NAND string.
Claim 18
Dependent Claim
34 words
The method of claim 15 wherein one of the different levels is ground, and another of the different levels is a voltage between ground and a programming voltage conveyed on a selected word line.
Claim 19
Independent Claim
102 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising: pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.
Claim 20
Independent Claim
102 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising: pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.
Claim 21
Independent Claim
96 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising: pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; wherein the programming voltage is within the range from 10 to 16 volts.
Claim 22
Independent Claim
96 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising: pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; wherein the programming voltage is within the range from 10 to 16 volts.
Claim 23
Dependent Claim
24 words
The method of claim 6 wherein the memory array comprises a two-dimensional memory array having one plane of memory cells formed in a substrate.
Claim 24
Dependent Claim
26 words
The method of claim 1 wherein the memory array comprises a three-dimensional memory array having at least two planes of memory cells formed above a substrate.
Claim 25
Dependent Claim
18 words
The method of claim 20 further comprising performing a read operation only after at least two programming pulses.
Claim 26
Dependent Claim
18 words
The method of claim 20 further comprising maintaining an inhibit voltage on associated array lines between programming pulses.
Claim 27
Dependent Claim
27 words
The method of claim 20 further comprising re-establishing a respective bias condition within selected and unselected NAND strings of a selected block before each such programming pulse.
Claim 28
Dependent Claim
47 words
The method of claim 20 further comprising: coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage; and de-coupling unselected NAND strings within the selected memory block from other associated array lines conveying bias voltages other than the inhibit voltage.
Claim 29
Dependent Claim
19 words
The method of claim 24 further comprising maintaining the inhibit voltage on the associated array lines between programming pulses.
Claim 30
Dependent Claim
60 words
The method of claim 24 further comprising: driving the selected word line to a voltage less than the programming voltage while unselected NAND strings are coupled to the associated array lines conveying the inhibit voltage; then decoupling the unselected NAND strings from the associated array lines conveying the inhibit voltage; and pulsing the selected word line to the programming voltage.
Claim 31
Dependent Claim
35 words
The method of claim 26 wherein: the selected word line is brought to ground before decoupling unselected NAND strings from the associated array lines conveying the inhibit voltage, and then driven to the programming voltage.
Claim 32
Dependent Claim
33 words
The method of claim 24 wherein the de-coupling unselected NAND strings step comprises turning off at least one of a plurality of series select devices at an end of the selected NAND strings.
Claim 33
Dependent Claim
24 words
The method of claim 28 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.
Claim 34
Dependent Claim
57 words
The method of claim 20 further comprising: coupling the selected NAND string to an associated array line conveying one of either a bit line programming voltage to program the selected memory cell or a bit line inhibit voltage to inhibit programming of the selected memory cell; and de-coupling the selected NAND string from other associated array lines.
Claim 35
Dependent Claim
34 words
The method of claim 30 wherein the de-coupling the selected NAND string step comprises turning off at least one of a plurality of series select devices at an end of the selected NAND strings.
Claim 36
Dependent Claim
24 words
The method of claim 31 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.
Claim 37
Dependent Claim
40 words
The method of claim 31 wherein the turning off step comprises driving to different levels respective select signals corresponding to at least two respective ones of the plurality of series select devices at the end of the selected NAND string.
Claim 38
Dependent Claim
34 words
The method of claim 33 wherein one of the different levels is ground, and another of the different levels is a voltage between ground and a programming voltage conveyed on a selected word line.
Claim 39
Dependent Claim
24 words
The method of claim 20 wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.
Claim 40
Dependent Claim
18 words
The method of claim 20 wherein the programming voltage is within the range from 10 to 16 volts.
Claim 41
Dependent Claim
21 words
The method of claim 20 wherein the substrate comprises a monocrystalline substrate including circuitry which is coupled to the memory array.
Claim 42
Dependent Claim
20 words
The method of claim 37 wherein NAND strings of a given memory plane include selection devices formed above the substrate.
Claim 43
Dependent Claim
25 words
The method of claim 1 wherein the modifiable conductance switch devices comprise transistors having a depletion mode threshold voltage at least some of the time.
Claim 44
Dependent Claim
44 words
The method of claim 1 wherein the modifiable conductance switch devices comprise devices chosen from the group consisting of: a device including a floating gate electrode; a device including silicon nanoparticles; a device including a polarizable material; and a device including a ferroelectric material.
Claim 45
Dependent Claim
17 words
The method of claim 6 wherein the modifiable conductance switch devices comprise thin film transistor (TFT) devices.
Claim 46
Dependent Claim
30 words
The method of claim 1 wherein the modifiable conductance switch devices have more than two nominal values of conductance, for storing more than one bit of data per memory cell.
Claim 47
Independent Claim
96 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising: pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; wherein the modifiable conductance switch devices comprise transistors having a charge storage dielectric.
Claim 48
Independent Claim
96 words
A method of operating an integrated circuit having a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said method comprising: pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; wherein the modifiable conductance switch devices comprise transistors having a charge storage dielectric.
Claim 49
Dependent Claim
15 words
The method of claim 43 wherein the charge storage dielectric comprises an oxide-nitride-oxide (ONO) stack.
Claim 50
Dependent Claim
22 words
The method of claim 43 wherein the transistors have a depletion mode threshold voltage for at least one of two data states.
Claim 51
Dependent Claim
92 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said modifiable conductance switch devices comprising thin film transistor (TFT) devices; array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block.
Claim 52
Dependent Claim
92 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices, said modifiable conductance switch devices comprising thin film transistor (TFT) devices; array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block.
Claim 53
Dependent Claim
26 words
The integrated circuit of claim 46 wherein the array support circuitry is further configured for performing a read operation only after at least two programming pulses.
Claim 54
Dependent Claim
26 words
The integrated circuit of claim 46 wherein the array support circuitry is further configured for maintaining an inhibit voltage on associated array lines between programming pulses.
Claim 55
Dependent Claim
35 words
The integrated circuit of claim 46 wherein the leakage current effects include changes in a voltage bias at one or more locations within a NAND string that otherwise may occur during a long programming pulse.
Claim 56
Dependent Claim
35 words
The integrated circuit of claim 49 wherein the array support circuitry is further configured for re-establishing a respective bias condition within selected and unselected NAND strings of a selected block before each such programming pulse.
Claim 57
Dependent Claim
111 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices; array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; and means for coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage to establish a bias condition within such unselected NAND strings.
Claim 58
Dependent Claim
111 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices; array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; and means for coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage to establish a bias condition within such unselected NAND strings.
Claim 59
Dependent Claim
27 words
The integrated circuit of claim 51 wherein the array support circuitry is further configured for maintaining the inhibit voltage on the associated array lines between programming pulses.
Claim 60
Dependent Claim
62 words
The integrated circuit of claim 51 further comprising: means for driving the selected word line to a voltage less than the programming voltage while unselected NAND strings are coupled to the associated array lines conveying the inhibit voltage; means for then decoupling, before the selected word line programming pulse, the unselected NAND strings from the associated array lines conveying the inhibit voltage.
Claim 61
Dependent Claim
21 words
The integrated circuit of claim 51 comprising a respective plurality of series select devices at an end of each NAND string.
Claim 62
Dependent Claim
30 words
The integrated circuit of claim 51 further comprising means for turning off at least one of a plurality of series select devices at an end of the selected NAND strings.
Claim 63
Dependent Claim
25 words
The integrated circuit of claim 54 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.
Claim 64
Dependent Claim
49 words
The integrated circuit of claim 46 further comprising means for coupling the selected NAND string to an associated array line conveying one of either a bit line programming voltage to program the selected memory cell or a bit line inhibit voltage to inhibit programming of the selected memory cell.
Claim 65
Dependent Claim
30 words
The integrated circuit of claim 57 further comprising means for turning off at least one of a plurality of series select devices at an end of the selected NAND strings.
Claim 66
Dependent Claim
25 words
The integrated circuit of claim 58 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.
Claim 67
Dependent Claim
38 words
The integrated circuit of claim 58 wherein the respective select signals corresponding to at least two respective ones of the plurality of series select devices at the end of the selected NAND string are driven to different levels.
Claim 68
Dependent Claim
35 words
The integrated circuit of claim 60 wherein one of the different levels is ground, and another of the different levels is a voltage between ground and a programming voltage conveyed on a selected word line.
Claim 69
Dependent Claim
100 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices; array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block, wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.
Claim 70
Dependent Claim
100 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices; array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block, wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.
Claim 71
Dependent Claim
94 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices; array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block, wherein the programming voltage is within the range from 10 to 16 volts.
Claim 72
Dependent Claim
94 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices; array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block, wherein the programming voltage is within the range from 10 to 16 volts.
Claim 73
Dependent Claim
25 words
The integrated circuit of claim 51 wherein the memory array comprises a two-dimensional memory array having one plane of memory cells formed in a substrate.
Claim 74
Dependent Claim
27 words
The integrated circuit of claim 46 wherein the memory array comprises a three-dimensional memory array having at least two planes of memory cells formed above a substrate.
Claim 75
Dependent Claim
35 words
The integrated circuit of claim 65 further comprising: means for performing a read operation only after at least two programming pulses; and means for maintaining an inhibit voltage on associated array lines between programming pulses.
Claim 76
Dependent Claim
30 words
The integrated circuit of claim 65 further comprising means for re-establishing a respective bias condition within selected and unselected NAND strings of a selected block before each such programming pulse.
Claim 77
Dependent Claim
52 words
The integrated circuit of claim 65 further comprising: means for coupling unselected NAND strings within a selected memory block to associated array lines conveying an inhibit voltage; and means for de-coupling unselected NAND strings within the selected memory block from other associated array lines conveying bias voltages other than the inhibit voltage.
Claim 78
Dependent Claim
22 words
The integrated circuit of claim 68 further comprising means for maintaining the inhibit voltage on the associated array lines between programming pulses.
Claim 79
Dependent Claim
62 words
The integrated circuit of claim 68 further comprising: means for driving the selected word line to a voltage less than the programming voltage while unselected NAND strings are coupled to the associated array lines conveying the inhibit voltage; means for then decoupling, before the selected word line programming pulse, the unselected NAND) strings from the associated array lines conveying the inhibit voltage.
Claim 80
Dependent Claim
20 words
The integrated circuit of claim 68 comprising a plurality of series select devices at an end of each NAND string.
Claim 81
Dependent Claim
25 words
The integrated circuit of claim 71 wherein the respective plurality of select devices and memory cell devices forming each NAND string are structurally substantially identical.
Claim 82
Dependent Claim
49 words
The integrated circuit of claim 65 further comprising: means for coupling the selected NAND string to an associated array line conveying one of either a bit line programming voltage to program the selected memory cell or a bit line inhibit voltage to inhibit programming of the selected memory cell.
Claim 83
Dependent Claim
39 words
The integrated circuit of claim 65 further comprising means for driving to different levels respective select signals corresponding to at least two respective ones of a plurality of series select devices at the end of the selected NAND string.
Claim 84
Dependent Claim
35 words
The integrated circuit of claim 74 wherein one of the different levels is ground, and another of the different levels is a voltage between ground and a programming voltage conveyed on a selected word line.
Claim 85
Dependent Claim
25 words
The integrated circuit of claim 65 wherein individual programming pulses are shorter than one microsecond, and the aggregate programming time is longer than ten microseconds.
Claim 86
Dependent Claim
19 words
The integrated circuit of claim 65 wherein the programming voltage is within the range from 10 to 16 volts.
Claim 87
Dependent Claim
22 words
The integrated circuit of claim 65 wherein the substrate comprises a monocrystalline substrate including circuitry which is coupled to the memory array.
Claim 88
Dependent Claim
21 words
The integrated circuit of claim 78 wherein NAND strings of a given memory plane include selection devices formed above the substrate.
Claim 89
Dependent Claim
13 words
The integrated circuit of claim 65 wherein the substrate comprises a polycrystalline substrate.
Claim 90
Dependent Claim
13 words
The integrated circuit of claim 65 wherein the substrate comprises an insulating substrate.
Claim 91
Dependent Claim
26 words
The integrated circuit of claim 46 wherein the modifiable conductance switch devices comprise transistors having a depletion mode threshold voltage at least some of the time.
Claim 92
Dependent Claim
42 words
The integrated circuit of claim 46 including modifiable conductance switch devices chosen from the group consisting of: a device including a floating gate electrode; a device including silicon nanoparticles; a device including a polarizable material; and a device including a ferroelectric material.
Claim 93
Dependent Claim
18 words
The integrated circuit of claim 51 wherein the modifiable conductance switch devices comprise thin film transistor (TFT) devices.
Claim 94
Dependent Claim
31 words
The integrated circuit of claim 46 wherein the modifiable conductance switch devices have more than two nominal values of conductance, for storing more than one bit of data per memory cell.
Claim 95
Dependent Claim
95 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices; and array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; wherein the modifiable conductance switch devices comprise transistors having a charge storage dielectric.
Claim 96
Dependent Claim
95 words
An integrated circuit comprising: a memory array including memory cells arranged in a plurality of series-connected NAND strings, said memory cells comprising modifiable conductance switch devices; and array support circuitry configured for pulsing a selected word line to a programming voltage a number of times to achieve an aggregate programming time for a selected memory cell, while limiting individual programming pulses to durations substantially less than the aggregate programming time, thereby limiting leakage current effects within NAND strings of a selected block; wherein the modifiable conductance switch devices comprise transistors having a charge storage dielectric.
Claim 97
Dependent Claim
16 words
The integrated circuit of claim 86 wherein the charge storage dielectric comprises an oxide-nitride-oxide (ONO) stack.
Claim 98
Dependent Claim
23 words
The integrated circuit of claim 86 wherein the transistors have a depletion mode threshold voltage for at least one of two data states.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-04-03 | 2009-10-03 | 2010-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-04-03 | 2013-10-03 | 2014-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-04-03 | 2017-10-03 | 2018-04-04 | $7700.00 | Window Closed / Lapsed |