Patent US6477084B2 successfully refreshed from Google Patents.
US6477084B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
NROM cell with improved programming, erasing and cycling
Assignee: Spansion Israel Ltd
•
Filing: 2001-02-07
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Granted: 2002-11-05
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Expires: 2021-02-07
Abstract
Abstract A nitride programmable read only memory (NROM) cell with a pocket implant self-aligned to at least one bit line junction. Alternatively, the bit line junction(s) can have a thin area of effective programming and erasing located nearby. Further alternatively, the channel can have a threshold voltage level implant which has a low voltage level in a central area of the channel and which has a peak of high voltage level near at least one of the bit line junctions. With one pocket implant, the NROM cell stores one bit. With two pocket implants, the NROM cell stores two bits.
Inventors
- 👤 Boaz Eitan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:22
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5671; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/0475; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/0413; H10D30/60; H10D30/69; H10D30/691; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
74 words
A nitride programmable read only memory (NROM) cell comprising: a channel; two diffusion areas on either side of said channel, each diffusion area having a junction with said channel; an ONO layer at least over said channel; a polysilicon gate at least above said ONO layer; wherein a programmed bit has negative charge and an erased bit has positive charge stored in portions of said ONO layer near at least one of said junctions.
Claim 2
Dependent Claim
74 words
A nitride programmable read only memory (NROM) cell comprising: a channel; two diffusion areas on either side of said channel, each diffusion area having a junction with said channel; an ONO layer at least over said channel; a polysilicon gate at least above said ONO layer; wherein a programmed bit has negative charge and an erased bit has positive charge stored in portions of said ONO layer near at least one of said junctions.
Claim 3
Dependent Claim
25 words
A cell according to claim 1 wherein the amount of negative charge to be stored is less than twice a standard unit of negative charge.
Claim 4
Dependent Claim
16 words
A cell according to claim 1 wherein a programmed bit has a reduced electric field therein.
Claim 5
Dependent Claim
20 words
A cell according to claim 1 and wherein said at least one of said junctions is both of said junctions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-04 | 2006-05-06 | 2006-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-04 | 2010-05-06 | 2010-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-04 | 2014-05-06 | 2014-11-05 | $7700.00 | Window Closed / Lapsed |